Abstract: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.

Abstract: In some embodiments, the present invention is directed to photovoltaic (PV) devices comprising silicon (Si) nanowires as active PV elements, wherein such devices are typically thin film Si solar cells. Generally, such solar cells are of the p-i-n type and can be fabricated for front and/or backside (i.e., top and/or bottom) illumination. Additionally, the present invention is also directed at methods of making and using such devices, and to systems and modules (e.g., solar panels) employing such devices.

Abstract: In a solid-state imaging device, the pixel circuit formed on the first surface side of the semiconductor substrate is shared by a plurality of light reception regions. The second surface side of the semiconductor substrate is made the light incident side of the light reception regions. The second surface side regions of the light reception regions formed in the second surface side part of the semiconductor substrate are arranged at approximately even intervals and the first surface side regions of the light reception regions formed in the first surface side part of the semiconductor substrate are arranged at uneven intervals, respectively, and the second surface side regions and the first surface side regions are joined respectively in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.

Abstract: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. In one embodiment, a photodiode array comprises a substrate having at least a front side and a back side, a plurality of diode elements integrally formed in the substrate forming the array, wherein each diode element has a p+ fishbone pattern on the front side, and wherein the p+ fishbone pattern substantially reduces capacitance and crosstalk between adjacent photodiodes, a plurality of front surface cathode and anode contacts, and wire interconnects between diode elements made through a plurality of back surface contacts.

Abstract: A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the signal charges and a second gate electrode formed at a second distance from the first impurity region for discharging unnecessary signal charges after extraction of a voltage signal from the first impurity region. The first distance between the first impurity region and the first gate electrode is larger than the second distance between the first impurity region and the second gate electrode.

Abstract: A thermopile infrared sensor array, comprises a sensor chip with a number of thermopile sensor elements, made from a semiconductor substrate and corresponding electronic components. The sensor chip is mounted on a support circuit board and enclosed by a cap in which a lens is arranged. The aim is the production of a monolithic infrared sensor array with a high thermal resolution capacity with a small chip size and which may be economically produced. The aim is achieved by arranging a thin membrane made from non-conducting material on the semiconductor substrate of the sensor chip on which the thermopile sensor elements are located in an array. Under each thermopile sensor element, the back side of the membrane is uncovered in a honeycomb pattern by etching and the electronic components are arranged in the boundary region of the sensor chip. An individual pre-amplifier with a subsequent low-pass filter may be provided for each column and each row of sensor elements.

Abstract: A semiconductor device includes a plurality of photoelectric conversion elements arranged in a region. A transfer transistor transfers an electrical charge of the photoelectric conversion elements. An amplifying transistor reads out the electrical charge. A reset transistor resets a gate electrical voltage of the amplifying transistor to a predetermined voltage. A plurality of wiring layers include at least a first wiring layer and a second wiring layer stacked on the first wiring layer. Each wiring layer includes at least one wiring, and is arranged over the region. The wirings of the first and second layers define an aperture of the photoelectric conversion elements.

Abstract: A pixel space is narrowed without increasing PN junction capacitance. A photoelectric conversion device includes a plurality of pixels arranged therein, each including a first impurity region of a first conductivity type forming a photoelectric conversion region, a second impurity region of a second conductivity type forming a signal acquisition region arranged in the first impurity region, a third impurity region of the first conductivity type and a fourth impurity region of the first conductivity type are arranged in a periphery of each pixel for isolating the each pixel, the fourth impurity region is disposed between adjacent pixels, and an impurity concentration of the fourth impurity region is smaller than an impurity concentration of the third impurity region.

Abstract: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first region, under an end of the gate electrode in a gate width direction.

Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device having a semiconductor element capable of reducing a cost and improving a throughput with a minute structure, and further, a method for manufacturing a liquid crystal television and an EL television. According to one feature of the invention, a method for manufacturing a semiconductor device comprises the steps of: forming a light absorption layer over a substrate, forming a first region over the light absorption layer by using a solution, generating heat by irradiating the light absorption layer with laser light, and forming a first film pattern by heating the first region with the heat.

Abstract: A photodiode designed to capture incident photons includes a stack of at least three superposed layers of semiconductor materials having a first conductivity type. The stack includes: an interaction layer designed to interact with incident photons so as to generate photocarriers; a collection layer to collect the photocarriers; a confinement layer designed to confine the photocarriers in the collection layer. The collection layer has a band gap less than the band gaps of the interaction layer and confinement layer. The photodiode also includes a region which extends transversely relative to the planes of the layers. The region is in contact with the collection layer and confinement layer and has a conductivity type opposite to the first conductivity type so as to form a p-n junction with the stack.

Abstract: The present invention provides a photoelectric conversion device in which a leakage current is suppressed. A photoelectric conversion device of the present invention comprises: a first electrode over a substrate; a photoelectric conversion layer including a first conductive layer having one conductivity, a second semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer over the first electrode, wherein an end portion of the first electrode is covered with the first semiconductor layer; an insulating film, and a second electrode electrically connected to the third semiconductor film with the insulating film therebetween, over the insulating film, are formed over the third semiconductor film, and wherein a part of the second semiconductor layer and a part of the third semiconductor layer is removed in a region of the photoelectric conversion layer, which is not covered with the insulating film.

Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.

Abstract: Methods include making a FinFET device structure having multiple FinFET devices (e.g. ntype and/or ptype) with different metal conductors and/or different high-k insulators in the gates formed on a SOI substrate. One such method includes removing a second semiconductor layer from a second metal layer in a region above a second cap layer, from adjoining regions and from regions adjacent to a second fin.

Abstract: The present invention relates to an optical device and to a method of fabricating the same. In embodiments, the invention relates to a photovoltaic device or solar cell. The optical device comprises a first electrode and a second electrode and an active element disposed between the first and second electrodes. The active element comprising a plurality of semiconducting structures extending in a lengthwise direction from the first electrode and being in contact with the first and second electrodes; the active element comprises an np-junction. For the semiconducting structures, at least a part of the structures is of a general plate or flake shape. In embodiments, the semiconducting structures have at least one characteristic dimension in the nanometer range.

Abstract: A solar cell array including a first solar cell with an integral bypass diode and an adjacent second solar cell and two discrete metal interconnection members coupling the anode of the bypass diode of the first cell with the anode of the second solar cell.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: Disclosed herein is a solid-state imaging element which includes a plurality of drive signal inputs, a plurality of bus lines, and a plurality of vertical transfer register electrodes. In the solid-state imaging element, a charge accumulated in light-receiving elements in a pixel region is vertically transferred by the drive signals input to the electrodes. Each of the electrodes has a contact part connected to the second contact and having a width smaller than a width of the electrodes in the pixel region, and a blank region is formed between predetermined adjacent two of the contact parts so that a width of the blank region is larger than a distance between respective two of the contact parts other than the predetermined adjacent two of the contact parts. The first contact is disposed on the blank region.

Abstract: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region for receiving photoelectric charges transferred by the plurality of transfer transistors; a rest transistor connected between a power supply voltage and the floating diffusion region for resetting the floating diffusion region by controlling a voltage loaded on the floating diffusion region in response to a second control signal; a drive transistor connected between the power supply voltage and the floating diffusion region to serve as a source follower buffer amplifier; and a select transistor connected between the drive transistor and a pixel output terminal for performing an addressing operation in response to a third control signal.

Abstract: A Silicon photodetector contains an insulating substrate having a top surface and a bottom surface. A Silicon layer is located on the top surface of the insulating substrate, where the Silicon layer contains a center region, the center region being larger in thickness than the rest of the Silicon layer. A top Silicon dioxide layer is located on a top surface of the center region. A left wing of the center region and a right wing of the center region are doped. The Silicon photodetector also has an active region located within the center region, where the active region contains a tailored crystal defect-impurity combination and Oxygen atoms.

Abstract: A photodiode and a method of fabricating a photodiode for reducing modal dispersion and increasing travel distance. The central region of the photodiode is made less responsive to incident light than a peripheral region of the photodiode. The less responsive central region discriminates the lower order modes such that only the higher order modes are incident on the more responsive peripheral region. Because the lower order modes are subtracted, the range of propagation constants is reduced and modal dispersion is also reduced.

Abstract: A solid state imaging device includes: an imaging region formed in an upper part of a substrate made of silicon to have a photoelectric conversion portion, a charge accumulation region of the photoelectric conversion portion being of a first conductivity type; a device isolation region formed in at least a part of the substrate to surround the photoelectric conversion portion; and a MOS transistor formed on a part of the imaging region electrically isolated from the photoelectric conversion region by the device isolation region. The width of the device isolation region is smaller in its lower part than in its upper part, and the solid state imaging device further includes a dark current suppression region surrounding the device isolation region and being of a second conductivity type opposite to the first conductivity type.

Abstract: An apparatus has multiple sets of independently addressable interdigitated nanowires. Nanowires of a set are in electrical communication with other nanowires of the same set and are electrically isolated from nanowires of other sets.

Abstract: A nanowire composite and a method of preparing the nanowire composite comprise a template having a plurality of hollow channels, nanowires formed within the respective channels of the template, and a functional element formed by removing a portion of the template so that one or more of the nanowires formed within the portion of the template are exposed. Since the nanowire composite can be prepared in a simple manner at low costs and can be miniaturized, the nanowire composite finds application in resonators and a variety of sensors.

Abstract: A multi-color photo sensor having a first photodiode with a first p-type layer and a first n-type layer, the first photodiode generates charge when illuminated with photons of a first wavelength range, a second photodiode with a second p-type layer and a second n-type layer, the second photodiode generates charge when illuminated with photons of a second wavelength range, and a readout integrated circuit electrically coupled to the first n-type layer of the first photodiode via a first metal interconnect and electrically coupled to the second n-type layer of the second photodiode via a second metal interconnect, the second metal interconnect traverses through the first photodiode to contact the second n-type layer of the second photodiode, the second metal interconnect is separated from the first photodiode by a first passivating insulator.

Abstract: A rear-illuminated-type photodiode array has (a) a first-electroconductive-type semiconductor substrate, (b) a first-electroconductive-type electrode that is placed at the rear side of the semiconductor substrate and has openings arranged one- or two-dimensionally, (c) an antireflective coating provided at each of the openings of the first-electroconductive-type electrode, (d) a first-electroconductive-type absorption layer formed at the front-face side of the substrate, (e) a leakage-lightwave-absorbing layer that is provided on the absorption layer and has an absorption edge wavelength longer than that of the absorption layer, (f) a plurality of second-electroconductive-type regions that are formed so as to penetrate through the leakage-lightwave-absorbing layer from the top surface and extend into the absorption layer to a certain extent and are arranged one- or two-dimensionally at the positions coinciding with those of the antireflective coatings at the opposite side, and (g) a second-electroconductive-t

Abstract: A photosensor includes a plurality of photosensitive regions including a first photosensitive region connected to a first voltage reference, and at least one additional photosensitive region. A signal collector is connected to the first photosensitive region. At least one switching device is for switching the at least one additional photosensitive region between the first voltage reference and a second voltage reference that is less than the first voltage reference, and for reversibly connecting the at least one additional photosensitive region to the signal collector so that the photosensor is variably responsive to different light levels.

Abstract: A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are expitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The expitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate silicon-based and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Geranium-On-Insulator (GeOI).

Abstract: An ultra high-resolution radiation detector and method for fabrication thereof, has a detector chip, comprising the so-called drift rings and an amplifier integrated with the diode component, centrally located n-type anode on one surface, the depletion region. The detector chip has a circular field of view, the depletion region which also has a circular field of view by ion implanting symmetrical p-n junctions on the surface of the radiation entrance side of the detector chip, said centrally n-type anode located on the opposite surface of the depletion region, and its position is in the region which outer of the depletion region, said centrally n-type anode was surrounded by a plurality of p-type drift electrode rings, which have an gibbous circularity topology; wherein the focus of said p-type drift electrode rings is the position of the anode, said FET (Field-Effect Transistor) was integrated in the position of the detector's anode and directly coupled to the detector's anode.

Abstract: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated inside the buried accumulation region. The resistance characteristic of the channel region changes in response to a field created by the charges accumulated in the accumulation region. Thus, when a voltage is applied to one side of the channel, the current read out from the other side is characteristic of the amount of stored charges.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: A semiconductor photodiode (18) is formed as a pn-junction between a region (2) of a first conductivity type and a region (6) of a second conductivity type. The region (6) of the second conductivity type is approximately hemispherical. A mini guard ring (8), i.e. a ring of the second conductivity type having a junction depth that is much smaller than the junction depth of the region (6) preferably surrounds the region (6) in order to prevent surface trapping. The photodiode (18) is operated with a high reverse bias so that light falling on the photodiode (18) produces the avalanche effect.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading gate. Therein, a groove is formed on the surface side of the substrate, and the transfer register and the reading gate are formed at the bottom part of the groove. With such a structure, in the solid-state image pickup device, reduction can be achieved for the smear characteristics, a reading voltage, noise, and others.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.

Abstract: Charge-splitting networks, optoelectronic devices, methods for making optoelectronic devices, power generation systems utilizing such devices and method for making charge-splitting networks are disclosed. An optoelectronic device may include a porous nano-architected (e.g., surfactant-templated) film having interconnected pores that are accessible from both the underlying and overlying layers. A pore-filling material substantially fills the pores. The interconnected pores have diameters of about 1-100 nm and are distributed in a substantially uniform fashion with neighboring pores separated by a distance of about 1-100 nm. The nano-architected porous film and the pore-filling, material have complementary charge-transfer properties with respect to each other, i.e., one is an electron-acceptor and the other is a hole-acceptor. The nano-architected porous, film may be formed on a substrate by a surfactant temptation technique such as evaporation-induced self-assembly.

Abstract: A photodetector arrangement has a semiconductor body with a substrate, and first, second and third layers. The first layer is located at the first main surface of the semiconductor body which is suited for reception of incident photon radiation which is to be detected. The second layer is located at the second main surface of the semiconductor body which is at a distance to the first main surface. The third layer is located between the substrate and the second layer.

Abstract: A solid state imaging device includes a substrate of a first conductivity type. A transistor, which includes a first gate electrode and a first and second impurity areas, is provided on a surface of the substrate. The first and second impurity areas are formed in the surface of the substrate and sandwich a region under the first gate electrode. A third impurity area of a second conductivity type is formed in the surface of the substrate and spaced from the second impurity area at an opposite side to the first gate electrode. A fourth impurity area is formed under the second impurity area and connected to the third impurity area. A second gate electrode is provided above the substrate. A fifth impurity area of the second conductivity type is formed in the surface of the substrate. The third and fifth impurity areas sandwich a region under the second gate electrode.

Abstract: A solid-state image pickup device 10 has an arrangement in which a second conductivity type semiconductor region 14 is formed on the surface of a first conductivity type electric charge accumulation region 13 of a light-receiving sensor portion, a shallow trench isolation layer 20 formed of an insulating layer is buried into a trench formed on a semiconductor substrate 11, the shallow trench isolation layer 20 is composed of an upper wide portion 21 and a lower narrow portion 22 and a second conductivity type semiconductor region 23 is formed around the lower narrow portion 22 of the shallow trench isolation layer 20. The solid-state image pickup device can suppress the occurrence of a dark current and a white spot, it can produce an image with high image quality and it can sufficiently maintain a sufficiently large amount of electric charges that can be handled by the light-receiving sensor portion.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: The present invention is a semiconductor module (20) in which, for example, twenty-five semiconductor devices (10) with a pnotoelectric conversion function are arranged in the form of a five row by five column matrix via an electrically conductive mechanism including of six connecting leads (21 to 26). The semiconductor devices (10) in each column are connected in series, and the semiconductor devices (10) in each row are connected in parallel. Positive and negative terminals, which are embedded in a light transmitting member (28) made of a transparent synthetic resin and which protrude to the outside, are also provided. The semiconductor device (10) comprises a diffusion layer, a pn junction, and one flat surface on the surface of a spherical p-type semiconductor crystal, for example.

Abstract: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without any conventional protective cover. The DLC film is less scratchable and less stainable. Since the fingerprint detection device has no protective cover, the device can be provided in a thin and compact form. In addition, the device has high reliability.

Abstract: Methods for passivating crystalline grains in an active layer for an optoelectronic device and optoelectronic devices having active layers with passivated crystalline grains are disclosed. Crystalline grains of an active layer material and/or window layer material are formed within the nanotubes of an insulating nanotube template. The dimensions of the nanotubes correspond to the dimensions of a crystalline grain formed by the deposition technique used to form the grains. A majority of the surface area of these grains is in contact with the wall of the nanotube template rather than with other grains.

Abstract: A particle, includes a semiconductor nanocrystal. The nanocrystal is doped.

Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.

Abstract: In a semiconductor module, twenty five semiconductor devices having light receiving properties, for example, are arranged in five by five matrices using a conductor mechanism formed from six lead frames Each column of semiconductor devices is connected in series and each row of semiconductor devices is connected in parallel. These are embedded in a light transmitting member formed from a transparent synthetic resin, and a positive electrode terminal and a negative electrode terminal are disposed. The semiconductor devices are formed with first and second flat surfaces, and negative electrodes and positive electrodes are disposed.

Abstract: On the front side of an n-type semiconductor substrate 5, p-type regions 7 are two-dimensionally arranged in an array. A high-concentration n-type region 9 and a p-type region 11 are disposed between the p-type regions 7 adjacent each other. The high-concentration n-type region 9 is formed by diffusing an n-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 as seen from the front side. The p-type region 11 is formed by diffusing a p-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 and high-concentration n-type region 9 as seen from the front side. Formed on the front side of the n-type semiconductor substrate 5 are an electrode 15 electrically connected to the p-type region 7 and an electrode 19 electrically connected to the high-concentration n-type region 9 and the p-type region 11.

Abstract: A vertical color filter sensor group formed on a substrate (preferably a semiconductor substrate) and including at least two vertically stacked, photosensitive sensors, and an array of such sensor groups. In some embodiments, a carrier-collection element of at least one sensor of the group has substantially larger area, projected in a plane perpendicular to a normal axis defined by a top surface of a top sensor of the group, than does each minimum-sized carrier-collection element of the group. In some embodiments, the array includes at least two sensor groups that share at least one carrier-collection element. Optionally, the sensor group includes at least one filter positioned relative to the sensors such that radiation that has propagated through or reflected from the filter will propagate into at least one sensor of the group.

Abstract: A solid state photovoltaic device is formed on a substrate and includes a photoactive channel layer interposed between a pair of electrodes. The photoactive channel layer includes a first material which absorbs light and operates as a hole carrier. Within the first material are nanoparticles of a second material which operate as electron carriers. The nanoparticles are distributed within the photoactive channel layer such that, predominantly, the charge path between the two electrodes at any given location includes only a single nanocrystal. Because a majority of electrons are channeled to the electrodes via single nanocrystal conductive paths, the resulting architecture is referred to as a channel architecture.