Abstract: At least one forward-biased semiconductor diode having a potential barrier is used as a temperature sensor whose sensitivity can be finely adjusted. An operational amplifier circuit (A1) is used to apply a bias voltage of DC or rectangular waveform to a semiconductor diode (D) having a potential barrier used as a temperature sensor. In view of the fact that the temperature sensitivity of the semiconductor diode (D) depends on the height of its potential barrier, the forward bias voltage applied from a bias circuit (2) directly to the semiconductor diode (D) is finely adjusted to obtain desired temperature sensitivity. The output voltage of the sensor is associated with a current, having an exponential temperature dependence, which flows in the semiconductor diode (D) with the forward bias being fixed.

Abstract: The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for receiving an integrated semiconductor component that will be examined, a heating element, and a temperature sensor. The temperature sensor has at least a portion of a parasitic functional element of the semiconductor component. As a result, reliability tests can be carried out in a particularly accurate and space-saving manner.

Abstract: To compensate for temperature dependent variations and process variations in surface resistance of a main resistor (R1) on a chip (1), one or more compensating resistors (R11, R12. . . R1n) can be connected in series with the first resistor (R1) via normally open switches (SR11, SR12. . . SR1n). The switches are closed to connect one or more of the compensating resistors (R11, R12. . . SR1n) in series with the main resistor (R1) in response to whether the voltage across resistors (R21, R22. . . R2n) produced on the chip (1) in the same process and proportional to the compensating resistors (R11, R12. . . R1n) is higher or lower than a fixed reference voltage (VR3).

Abstract: A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or AlxGa1−xN(x>0.69) connected by electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W2C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W2C adhesive layer, or an adhesive layer with an overlay metallization having a thermal coefficient of expansion not greater than about 3.5 times that of the adhesive layer. The device can be encapsulated with a reacted borosilicate mixture, with or without an upper die which helps to hold on lead wires and increases structural integrity. Applications include temperature sensors, pressure sensors, chemical sensors, and high temperature and high power electronic circuits.

Abstract: In a semiconductor device in which a plurality of electro-thermal conversion elements and a plurality of switching devices for flowing electric currents through the plural electro-thermal conversion elements are integrated on a first conductive type semiconductor substrate, the switching devices are insulated gate type field effect transistors severally comprising: a second conductive type first semiconductor region formed on one principal surface of the semiconductor substrate; a first conductive type second semiconductor region for supplying a channel region, the second semiconductor region being formed to adjoin the first semiconductor region; a second conductive type source region formed on the surface side of the second semiconductor region; a second conductive type drain region formed on the surface side of the first semiconductor region; and gate electrodes formed on the channel region with a gate insulator film put between them; and the second semiconductor region is formed by a semiconductor having a

Abstract: A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

Abstract: A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes.

Abstract: A semiconductor device 14 capable of reducing the warpage in a substrate is provided. A semiconductor chip 12 is mounted on a substrate 10 made of an electro-insulating material by flip-chip bonding, so that connector terminals formed on the substrate 10 are connected to electrodes of the semiconductor chip 12 and a gap between the substrate 10 and the semiconductor chip 12 is filled with an underfiller 18. According to the present invention, in the semiconductor device 14, none of sides of the substrate 10 is parallel to any one of sides of the semiconductor chip 12, and none of diagonal lines S of the substrate 10 coincides with any one of diagonal lines T of the semiconductor chip 12.

Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Abstract: The invention concerns an analysis device including at least one chip (110) equipped with a plurality of analysis electrodes (112). In accordance with the invention, the device also includes means of individual heating (150) of the analysis electrodes. The invention can be used for the analysis of chemical or biological products, for example in an antigen/antibody recognition or DNA/DNA analysis.

Abstract: A heat resisting resin sheet is bonded to a semiconductor chip as a protective cap for protecting a beam structure provided on the semiconductor chip, through a heat resisting adhesive. The heat resisting resin sheet is composed of a polyimide base member and the heat resisting adhesive is composed of silicone adhesive. The heat resisting resin sheet is not deformed during a manufacturing process of the semiconductor chip. In addition, grinding water does not invade into the semiconductor chip during dicing-cut.

Abstract: A thin-film thermocouple is provided which can be used at temperature of up to 900.degree. C. The thin-film thermocouple includes: a silicon substrate; an SiO.sub.2 diffusion barrier layer formed on the substrate; a titanium oxide adhesion layer formed on the diffusion barrier layer; a palladium thin film formed on the diffusion barrier layer; and a platinum thin film formed on the diffusion barrier layer and overlapping a portion of the palladium thin film to form a thermocouple junction.

Abstract: This invention relates to a high-transimpedance solid-state switch manufactured by micromachining technology. A thermopile is formed by a thin-film structure capable of producing sufficient thermoelectrical voltage to drive a MOS transistor on and off, functioning like a switch. The driving thermoelectric voltage is generated by Joule's heat released by a thin-film heater disposed nearby a thermopile hot junction to generate a substantial temperature difference related to its cold junction. These elements can be monolithically integrated, wherein the heater and hot junctions are disposed on a thermal pad formed by micromachining having high thermal isolation.

Abstract: A diode suited for absorbing a surge which includes a semiconductor substrate, a pn junction defined in the semiconductor substrate, and an exothermic body adjacent to the pn junction which leads the pn junction to the Zener breakdown under an overcurrent is disclosed. This diode is improved in a characteristic against a surge utilizing the secondary breakdown and prevents the yield from lowering due to inconstancy in resistivity of the wafer used.

Abstract: In a photoelectric conversion device including peripheral ICs, the peripheral ICs are in thermal contact with a substrate having photoelectric conversion elements and a chassis, which covers the peripheral ICs and has high thermal conductivity, via a thermal conductive member, so as to eliminate adverse influences of heat produced by the peripheral ICs such as a low S/N ratio.

Abstract: A monolithic, integrated semiconductor circuit comprising a high-voltage ice (210) with a predetermined reverse-conduction threshold comprising a chain of zener diodes (220-240). Device 210 is connected in series with a thermal compensation device (250) constituted by a plurality of Vbe multipliers connected in series with one another. Each of the Vbe multipliers is formed by a resistive divider (R1i, R2i) and a low-voltage transistor (Ti) or two or more low-voltage transistors in a Darlington configuration.

Abstract: A field effect transistor (10) for chemical sensing by measuring a change in a surface potential of a gate electrode (48) due to exposure to a fluid has a semiconductor substrate (12) with a trench (18,20). The trench has a first sidewall (30) and a second sidewall (32) disposed opposite the first sidewall to provide a fluid gap (50) for the fluid to be sensed. The gate electrode is disposed overlying the first sidewall of the trench, and a source region (54) and a drain region (56) are disposed in the second sidewall of the trench. A channel region (52) is disposed between the source and drain regions, and the gate electrode is disposed opposite the first channel region across the fluid gap. A heater (26) for regulating the temperature of the gate electrode is disposed in the first sidewall of the trench.

Abstract: A thermoelectric material which exhibits a high thermoelectric performance even at high temperatures is shown and described. A thermoelectric material is provided with a plurality of conductive layers made of a first semiconductor only and a plurality of barrier layers made of a second semiconductor only, which are alternatingly arranged, a diffusion-preventive layer being interposed between neighboring conductive layers and barrier layers. Diffusion between the conductive layers and the barrier layers under high-temperature conditions is prevented, and the thermoelectric material maintains high performance standards at high temperatures.

Abstract: The object of the present invention is to provide a temperature detecting method wherein a temperature detecting diode is formed in the proximity of and thermally coupled to an object of temperature detection element in the form of a semiconductor element so that, even when a high power is instantaneously applied, the temperature of the object element for temperature detection can be detected with a high degree of accuracy.

Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Abstract: A temperature controlled cryogenic package system for efficiently and precisely monitoring and controlling the operating temperature of a high temperature superconductor circuit placed on a substrate. The cryogenic package system comprises a heating element formed on the same substrate as the high temperature superconductor circuit, a control circuit capable of activating and deactivating the heating element, and a temperature sensor placed in thermal proximity to the high temperature superconductor circuit. The temperature sensor monitors the operating temperature of the high temperature superconductor circuit, and conveys temperature information to the control circuit. The control circuit activates or deactivates the heating element according to the warming or cooling effect that is necessary in order to maintain the high temperature superconductor circuit within a predetermined temperature range, where the range of temperature fluctuation is within plus or minus 0.1 K of a predetermined temperature.

Abstract: In a photoelectric conversion device including peripheral ICs, the peripheral ICs are in thermal contact with a substrate having photoelectric conversion elements and a chassis, which covers the peripheral ICs and has high thermal conductivity, via a thermal conductive member, so as to eliminate adverse influences of heat produced by the peripheral ICs such as a low S/N ratio.

Abstract: Thermally isolated circuit formed on a semiconductor on insulator structure includes a semiconductor surrounded by a semiconductor outer portion with an insulator therebetween. A cavity formed in the underlying semiconductor substrate opposite to the island provides thermal isolation.

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material.In said pocket are included a type N+ cathode region and a type P anode region enclosing it.The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.

Abstract: A circuit substrate includes a plurality of semiconductor devices including electrodes, a wiring having a plurality of branched portions and mainly formed of a metal material, a terminal for applying a voltage to the wiring to anodize the branched portions, and an anodization controller for controlling degrees of anodization of the branched portions. The branched portions serve as the electrodes of the semiconductor devices. The terminal is connected to the wiring.

Abstract: In a semiconductor protection circuit, a current fuse and a transistor are connected in series between a power supply terminal and a ground. A bias circuit is provided between the base and the emitter of the transistor. The bias circuit applies between the base and the emitter of the transistor a constant bias voltage that is lower than a normal environment temperature forward voltage of a p-n junction between the transistor's base and emitter. When a load connected to the other terminal of the current fuse is overheated, the forward voltage of the p-n junction drops, and the transistor is turned on.

Abstract: In a method for producing a diode, a first, strongly positively doped silicon wafer is bonded in accordance with the silicon fusion method to a second, weakly negatively doped silicon wafer, and subsequently the weakly negatively doped second silicon wafer is ground down to a predetermined thickness. A chromium layer which contains a small percentage of arsenic is used for resistive contact-making on the negatively doped second silicon wafer. In this way, a diode is obtained which has a small forward voltage in conjunction with a precise breakdown voltage.

Abstract: A sensor (10) includes a gate electrode (20) overlying a channel region (34). A gap (22) between the gate electrode (20) and the channel region (34) allows a surface (28) of the gate electrode (20) to be exposed to a chemical. Upon exposure to the chemical, a surface potential or an electrical impedance of the gate electrode (20) may change. Comparing the changes in surface potential versus the changes in electrical impedance provides a method to distinguish between similar chemical species and also to extend the detection range of the sensor (10).

Abstract: A semiconductor-on-insulator structure includes a single crystal semiconductor substrate, an insulating layer on the single crystal semiconductor substrate, a recrystallized single crystal semiconductor layer on the insulating layer and having a subgrain, i.e., quasi grain boundary and a highly doped region including the quasi grain boundary and having a higher dopant impurity concentration than other parts of the single crystal semiconductor layer. Thus, a non-uniformity in the resistance is suppressed without reducing the piezoresistance effect of the structure.

Abstract: A temperature compensated logarithmic detector biased with a proportional to absolute temperature (PTAT) voltage produced in accordance with an area ratio of biasing transistors is disclosed. According to one implementation of the invention, the temperature compensated logarithmic detector includes biasing circuitry and a logarithmic detector cell. The biasing circuitry receives an input signal and produces a PTAT bias voltage from the input signal. The PTAT characteristic of the PTAT bias voltage is produced by an area ratio. The logarithmic detector cell converts the input signal to a logarithmic output signal in accordance with a logarithmic transfer function over a narrow range.

Abstract: The subject matter of the application is directed to a power semiconductor component, whereby, in addition to a load transistor, a plurality of transistors and resistors are monolithically integrated and form respective current mirrors together with the load transistor. Advantageously, resistors of polysilicon are produced simultaneously with gate electrodes, and resistors of aluminum are produced simultaneously with a contacting layer. A largely independent measurement of the load current, of the semiconductor temperature, and of the saturation voltage of the load transistor as well as an improvement in the measuring precision are possible as a result of the subject matter of the application.

Abstract: A biomedical sensor (20) is formed on a semiconductor substrate (22). Insulated dielectric layers (23, 24) are formed on the face and backside of the semiconductor substrate (22). Metal leads (26, 28) contact the substrate (22) through openings in the dielectric layer (23). The leads (26, 28) are also each connected to a set of interleaved longitudinal contact fingers (27, 29). A pair of contacts (30, 32) are formed on the opposite side of the substrate (22) from the contact figures (27, 29). A conductive biologic sample is placed over the interleaf fingers (27, 29), electrical measurements can be made through backside contacts (30, 32) so resistance measurements can be taken.

Abstract: A thermal picture synthesis device (1) of multi-layer construction has a resistor element (3) spaced from a semi-conductor substrate layer (2). The resistor element (3) is made of titanium or Ni-chrome. A drive element layer (4) is provided either in or attached to the substrate layer (2) for the resistor element (3). By placing the drive element layer parallel to and spaced from the resistor element (3) it is possible to pack a plurality of resistor elements (3) into a side by side adjacent array with a high fill factor or packing density and this coupled with the use of titanium or Ni-chrome for the resistor elements (3) and the spacing of these elements from the semi-conductor substrate (2) allows the device to operate at a higher apparent temperature than is conventional.

Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.

Abstract: A chemical probe field effect transistor (10) for measuring surface potential as a function of temperature and used for chemical sensing. Source and drain regions (14, 16) in a semiconductor substrate (12) define a channel region (34). A gate insulating layer (18) covers the channel region, and a gate electrode layer (20) is disposed above the gate insulating layer to provide a gap (22) between the gate insulating layer and the gate electrode layer. This gap permits a fluid to contact an exposed surface (28) of the gate electrode layer. A heating layer (30) is disposed overlying the gate electrode layer to regulate its temperature. The surface potential of the gate electrode layer changes in response to the presence of certain chemicals in the contacting fluid.

Abstract: Device to monitor and control the temperature of electronic chips to enhance reliability including a thermal electric cooling device in which the cold side is thermally secured to the chip and the hot side is attached to a heat sink. A thermocouple is sandwiched between the TEC device and the chip and a feedback control circuit is connected between the thermocouple and the voltage source which applies a potential to the TEC device to maintain the chip at the desired substantially constant temperature.

Abstract: A plurality of Zener diodes are connected between two electrodes of a transistor as the protector of the transistor to obtain a predetermined breakdown voltage. Each Zener diode has a breakdown of 5 V whose temperature coefficient is substantially zero.

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Abstract: In a semiconductor device with a power element on a substrate, a temperature monitor element is formed on the same substrate. In case of thermal overload in the power element, a signal from the temperature monitor element can be used for turning the power element off. For enhanced temperature response, the temperature monitor element is in part surrounded by the power element or/and disposed beneath an integrated, thermally conductive extension of an electrode of the power element.

Abstract: A frequency stable oscillating device includes an oscillating transistor. A heating element is disposed in close proximity to the oscillating transistor. A temperature sensor is mounted in close proximity to the oscillating transistor. A temperature control device supplies a variable signal which is dependant upon a local temperature of the oscillating transistor, wherein the variable signal controls the operation of the heating element. The heating element may alternately consist of one or more resistive patches, or one or more heating transistors which are biased to provide sufficient heating. The oscillating device may be formed from either IC or MMIC technologies, and may be formed from either silicon or GaAs.

Abstract: A two-way conductive directional circuit formed in a polycrystalline silicon layer separated by an insulation film from a semiconductive element is one-way biased for sensing a temperature of the semiconductive element. The directional circuit may be provided with a bias in either conductive direction thereof for sensing a temperature of the semiconductive element, before being provided with a bias in the other conductive direction thereof for sensing the temperature of the semiconductive element.

Abstract: A double-sided oscillator package and method of coupling components thereto. A package 100 having an open-top receptacle adapted to receive electronic components and an open-bottom receptacle 114 adapted to receive a piezoelectric element and a cover 116 for hermetically sealing the open-bottom receptacle 114. The electronic components and piezoelectric element are electrically connected. A hermetic environment 118 is established by coupling the cover 116 and open-bottom receptacle 114.

Abstract: A semiconductor switch includes a power FET and a temperature sensor for providing a control signal to switch off the power FET when it reaches a predetermined thermal condition, such as a particular temperature. The power FET consists of a semiconductor body having a first region (13) of a first conductivity type adjacent one major surface (10a) thereof, and a plurality of cells (11). Each such cell has a second region (32) of the second (opposite) conductivity type provided within the first region (13), a third region (33) of the first conductivity type formed within the second region (32), and an insulated gate overlying a conduction channel in the second region (32) between the first and third regions (33 and 13). The temperature sensor (2) is formed within the semiconductor body (10) and consists of a number of further cells (11') of the same structure as the cells (11) of the power FET.

Abstract: An integrated circuit having a semiconductor layer having formed therein a electronic circuit. An electrical device, electrically connected to the electronic circuit, has a corrugated platform supported over, displaced from, and integrally formed with, the substrate. In a preferred embodiment the electrical device is a bolometer and the electronic circuit is a read out circuit for the device. The platform includes a surface member and a leg, a proximate end of the leg being disposed on the substrate and the distal end being elevated from the substrate and terminating at the surface member. Preferably the leg and the surface member are corrugated. The supporting surface has a corrugation parallel with the leg. The surface member is supported, as a corrugated air-bridge, over the surface of the substrate by corrugated legs. The temperature sensitive resistive material is formed over the corrugated surface member.

Abstract: This invention relates to a power semiconductor device with a temperature sensor (32). The power semiconductor device (36), such as a power transistor, comprises a plurality of power device cells (108). The temperature sensor comprises a temperature sensing diode (34) implemented in at least one of the power device cell (108) such that the power device cell and sensing diode have a common conduction region (102), whereby the temperature sensor can directly sense the temperature of the power device cell.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: In the conventional thermoelectric conversion module, P-type thermoelectric semiconductor chips and N-type thermoelectric semiconductor chips are alternately arranged in both the longitudinal and the transverse directions. Consequently, assembling work is complicated and there arises the problem in quality that erroneous types of chips are arranged. In the present invention, therefore, each of either rows of chips or columns of chips is constituted by thermoelectric semiconductor chips of the same type, thereby to improve assembling workability as well as to prevent erroneous arrangement. Furthermore, as a preferred fabricating method, bar-shaped thermoelectric semiconductors are used and are jointed to one substrate and then, are electrically disconnected between the leads.

Abstract: A semiconductor component is formed by an insulated gate field effect device having a semiconductor body with a first region of one conductivity type adjacent one major surface, a second region defining a conduction channel area separating a third region from the first region, an insulated gate adjoining the conduction channel area for controlling current flow between the first and third regions and an injection region for injecting opposite conductivity type charge carriers into the first region, and a protection device for limiting the current through the insulated gate field effect device. The protection device is formed by a fourth region of the opposite conductivity type formed within the first region, a fifth region separated from the first region by the fourth region, a first conductive path connecting the fifth region to the insulated gate for allowing the flow of one conductivity type charge carriers towards the insulated gate and a second conductive path connected to the fourth region.

Abstract: A hybrid infrared focal plane array detector employs a detector layer and transparent substrate bonded to a thin semiconductor readout integrated circuit and thicker readout circuit substrate. The readout circuit is rigidly bonded to the readout substrate to form a composite structure having a thermal coefficient of expansion substantially matching that of the detector portion. The hybrid device may be cooled from room temperature to cryogenic operation temperatures without thermal mismatch structural problems.