Abstract: A first guard ring formed by high concentration ion diffusion is established around the transistor formation region of the semiconductor substrate. A second guard ring is established around the first guard ring with a prescribed gap therebetween. A metal film is formed opposing to each guard ring with an insulating film interposed therebetween; these metal films are connected to the opposing guard rings by interlayer wires. The metal films are each connected to external terminals providing a standard potential by individual metal wires from their respective electrodes.

Abstract: A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of adjustment structures and of a chipping stopper with an edge passivation containing a-C:H or a-Si. In this manner, the high-voltage diode is inexpensive to manufacture. The diode has a rating for reverse voltages of, in particular, above about 400 V and preferably above about 500 V, and can be fabricated with the least possible process complexity and thus a small number of photo technologies and, in the edge region, can readily be equipped with a channel stopper for avoiding leakage currents and a chipping stopper for limiting the extent of saving defects.

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor regionm. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.

Abstract: Besides the central pn-junction and the central electrode, a PD chip has a peripheral pn-junction and a peripheral electrode which do not appear on the sides. The ends of the peripheral pn-junction are covered with a protection layer for preventing self-shortcircuit. A reverse bias is applied to the peripheral electrode for making a wide depletion layer beneath the peripheral pn-junction. Extra carriers generated by peripherally-incidence rays are fully absorbed by the peripheral depletion layer and annihilated by the reverse bias.

Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.

Abstract: A lateral semiconductor element (10) in thin-film SOI technology comprises an insulator layer (14) which rests on a substrate (12) and is buried under a thin silicon film (16), on top of which the source, or anode, contact (18) and the drain, or cathode, contact (22) are mounted. The anode contact (18) and the cathode contact (22) each lie over separate shield regions (28,30) within substrate (12), with the anode contact (18) being electrically connected with substrate (12).

Abstract: A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones of a second, opposite conductivity type are embedded in the interface region between the semiconductor substrate and the at least one layer. The floating semiconductor zones are dimensioned such that the dimension of a semiconductor zone is do small compared to the layer thickness of the at least one semiconductor layer and is essentially equal to or less than a distance between the floating semiconductor zones in the interface region.

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.

Abstract: An n+ type emitter region and a p-type base region are formed in contact with one main surface of an n-type collector region, a p-type cathode region is formed in a ring shape in contact with the main surface so as to enclose the emitter region and the base region, the potential at the cathode region is sustained at a level equal to the potential at the emitter region and a p-type guard ring region is formed in a ring shape so as to enclose the cathode region. This structure prevents the base drive circuit from becoming damaged by an avalanche breakdown current.

Abstract: The present invention relates to an improved method of forming and structure for under bump metallurgy (“UBM”) pads for a flip chip which reduces the number of metal layers and requires the use of only a single passivation layer to form, thus eliminating a masking step required in typical prior art processes. The method also includes repatterning bond pad locations.

Abstract: To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n− layer, and a termination region is formed on the surface of the above n− layer. An impurity concentration ratio between the n− layer and the n-layer is less than 1:2, and the thickness of the n− layer is less than that of a source n+ layer. Reliability can be secured even in a high temperature operation.

Abstract: A first guard ring formed by high concentration ion diffusion is established around the transistor formation region of the semiconductor substrate. A second guard ring is established around the first guard ring with a prescribed gap therebetween. A metal film is formed opposing to each guard ring with an insulating film interposed therebetween; these metal films are connected to the opposing guard rings by interlayer wires. The metal films are each connected to external terminals providing a standard potential by individual metal wires from their respective electrodes.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering.

Abstract: In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate's surface beneath the field insulation film, field limiting rings (FLRS) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape.

Abstract: A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surface (S2) of the semiconductor substrate (1) corresponding to a beveled surface. The P layer (23) surrounds the P layer (22) in non-contacting relationship with the P layer (22). A separation distance (D) between the P layers (22, 23) is set at not greater than 50 &mgr;m. A distance (D23) between a third surface (S3) of the semiconductor substrate (1) and a portion of the P layer (23) which is closer to the third surface (S3) is less than a distance (D22) between the third surface (S3) and a portion of the P layer (22) which is closer to the third surface (S3).

Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.

Abstract: A silicon-based semiconductor component includes a high-efficiency barrier junction termination. In the semiconductor component, a silicon semiconductor region takes on the depletion region of an active area of the semiconductor component. The junction termination for the active area is formed with silicon with a doping that is opposite to that of the semiconductor region, and the junction termination surrounds the active area on or in a surface of the semiconductor region. The junction termination is doped with a dopant that has a low impurity energy level of at least 0.1 eV in silicon. Preferably Be, Zn, Ni, Co, Mg, Sn or In are used as acceptors and S, Se or Ti are provided as donors.

Abstract: The active area of a semiconductor die is surrounded by a plurality of concentrically spaced ring shaped P type diffusions. The diffusions have a low concentration produced by a total boron implant dose of from about 2E12 to 5E13 atoms/cm2. Four to twelve rings are used to terminate an active area at a potential of 600 to 1200 volts with respect to the die street.

Abstract: Besides the central pn-junction and the central electrode, a PD chip has a peripheral pn-junction and a peripheral electrode which do not appear on the sides. The ends of the peripheral pn-junction are covered with a protection layer for preventing self-shortcircuit. A reverse bias is applied to the peripheral electrode for making a wide depletion layer beneath the peripheral pn-junction. Extra carriers generated by peripherally-incidence rays are fully absorbed by the peripheral depletion layer and annihilated by the reverse bias.

Abstract: A field effect transistor having a high breakdown withstand capacity is provided. An active region 7a is surrounded by a fixed potential diffusion layer 16, and a channel region 15 is formed in the active region 7a. A gate pad 35 is provided outside the fixed potential diffusion layer 16. Minority carriers injected at a peripheral region of the active region 7a flow into the fixed potential diffusion layer 16, which prevents breakdown attributable to concentration of the carriers. The fixed potential diffusion layer 16 is surrounded by a plurality of guard ring diffusion layers 171 through 174, and a pad diffusion layer 18 formed in a position under the gate pad 35 is connected to the innermost guard ring diffusion layer 171. Since this encourages expansion of a depletion layer under the gate pad 35, an increased breakdown voltage is provided.

Abstract: An electrical contact, preferably made from a gold-plated, beryllium-copper flat stock which allows radio-frequency signal to pass with low noise, is provided within a housing. The electrical contact has two arms for contact with two external circuits. The electrical contact further has a pivot for allowing the electrical contact to adjust within the housing. The housing supports the electrical contact and is provided with a pivot point, such as a non-conducting rubber tip, for meeting the pivot of the electrical contact. The housing combined with one or more of the electrical contacts results in a testing port especially suited for providing high frequency communication between an electrical testing fixture and a device under test, such as a high-frequency hybrid integrated circuit.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed on a semiconductor substrate including an isolation diffusion region around the semiconductor device, a substrate layer, an epi layer on top of the substrate layer, a surface diffusion region extending into the epi layer from a top surface of the epi layer and a metallization line coupled to the surface diffusion, wherein the metallization line traverses the semiconductor device and the isolation diffusion region. The semiconductor device also includes a poly field plate over the isolation diffusion region and beneath the metallization line, a field limiting diffusion region provided in the epi layer between the surface diffusion region and the isolation diffusion region and below the metallization line, and a contact coupled to the field limiting diffusion region, wherein the contact extends to a region below the metallization line and overlapping the poly field plate.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed on the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge passivation zone comprising a junction termination extension (JTE) JTE region that includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at a point substantially directly beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point, becoming less in both the portions extending away from and beneath the well region.

Abstract: A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity type as the collector region is formed spaced from the pn junction and at a dose higher than that of the collector region. A field plate overlaps the pn junction and the accelerating region. The field plate has an edge portion that extends past the accelerating region. When a voltage of a reverse direction is applied to the pn junction, an electric field becomes concentrated on the accelerating region as well as on the pn junction and on the edge portion of the field plate. This increases an electric field distribution area and thus also increases the breakdown voltage.

Abstract: A high voltage semiconductor device is provided with a p layer which forms a main pn-junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n− layer through an insulating film, the area of the field plates being not less than one half of the n− surface. This arrangement is particularly effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

Abstract: An anode electrode metal layer composed of aluminum is formed in a region on the inner side than an anode layer formed on a main surface of a semiconductor substrate. Thus, an impurity diffusion region from the innermost circumferential surface of said surface of field limiting innermost circumferential layer to the outermost circumferential surface of the anode electrode metal layer may be used as an electrical resistance. As a result, the hole density distributed from the bottom side of the field limiting innermost circumferential layer to a cathode layer when forward bias is applied may be reduced. As a result, when a reverse bias is applied, locally great recovery current passed from a cathode layer to the bottom of field limiting innermost circumferential layer may be restrained. Therefore, a diode capable of preventing destruction of a field limiting innermost circumferential layer when a reverse bias is applied may be provided.

Abstract: A high-voltage SOI thin-film transistor includes a semiconductor thin film of a first conductivity type which is embedded in an insulator layer disposed on a semiconductor body. The semiconductor thin film includes a drain zone and a source zone, both having a second conductivity type opposite the first conductivity type. A gate electrode is also provided in the insulator layer. Field plates are disposed obliquely in the insulator layer between the gate electrode and the drain zone, in such a way that their spacing from the semiconductor thin film increases with increasing distance from the gate electrode. Highly doped zones of the second conductivity type in the semiconductor thin film are associated with the field plates, so that when a space charge zone is propagating from the source zone, a voltage at the various field plates stops changing and remains the same.

Abstract: The breakdown strength of a lateral diode using a field plate is improved. There are provided a track-like first field plate connected to an anode electrode, a track-like second field plate formed outside the first field plate and connected to a cathode electrode, track-like third field plates provided concentrically between the first and second field plates, and fourth field plates provided so as to cross the first to third field plates and connected to each of them. The fourth field plates are so positioned that they allow more current to flow in the corner sections and under the electrodes where an electric field is liable to concentrate.

Abstract: A semiconductor integrated circuit is made up of a plurality of input-output circuit portions which are aligned at irregular intervals between a core portion and an external portion, a first guard-ring which is formed in the respective input-output circuit portions, and a second guard-ring which is formed between the respective input-output circuit portions. Accordingly, the semiconductor integrated circuit can prevent latch-up between the respective input-output circuit portions without changing the layout of the respective input-output circuit portions.

Abstract: The arrangement with a pn-junction and the measure for reducing the risk of a breakdown of the junction is composed of a combination of a field plate (4) and a stop electrode respectively having a multi-step edge section (40 or, respectively, 50) with a JTE technique, as a result whereof blocking voltages clearly above 2500 Volts can be achieved given slight space requirement.

Abstract: A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least a buried layer of second conductivity type selectively formed in the semiconductor layer, extending at substantially right angles to a line connecting the first and second main electrodes, comprising a plurality strips functioning as current paths and set at a potential different from a potential of any other electrode when a depletion layer extending from a region near the first main electrode reaches the buried layer.

Abstract: A resistor on a semiconductor wafer comprising a silicon substrate, a first doped layer in a predetermined area on the silicon substrate, a second doped layer within a predetermined area of the first doped layer, a dielectric layer above the first and second doped layers on the silicon substrate, a passivation layer on the dielectric layer, and a conducting layer between the dielectric layer and the passivation layer. The silicon substrate contains dopants that characterize it as an n-type (or p-type) semiconductor. The first doped layer functioning as a resistor layer is a p-type (or n-type) semiconductor and forms a first pn-junction at its interface with the silicon substrate to prevent electrical leakage. The second doped layer is a n-type (p-type) semiconductor and forms a second pn-junction at its interface with the first doped layer that prevents electrical leakage. The passivation layer has a plurality of charges at fixed positions.

Abstract: A multi guard ring structure for a reach-through type semiconductor device has at least first and second guard ring regions. The first guard ring region surrounds a main region with a predetermined first spacing. The second guard ring region surrounds the first guard ring region with a predetermined second spacing. To improve the ability to withstand reverse bias voltage, the second spacing between the first and second guard ring regions is made smaller than the first spacing between the main region and the first guard ring region in order that a maximum value of an electric field strength at a junction between the first guard ring region and the drift region may be equal to or lower than 85% of a maximum value of a field strength at the main junction at the avalanche breakdown condition of the main junction.

Abstract: A high voltage semiconductor device having an improved junction termination extension for increasing the surface breakdown junction voltage. The device comprises a semiconductor substrate (10) of a first electrical conductivity type having a major surface (24) with an edge (26). The substrate has a first impurity region (22) of a second electrical conductivity type formed therein and having a first doping concentration and a second impurity region (28) of a said second electrical conductivity type, having a second doping concentration less than the first doping concentration, formed in the substrate between the first impurity region and the edge, and a field shield plate (30) disposed on the major surface in conductive relation with the first impurity region. The first field shield plate has an outer edge which terminates above the second impurity region.

Abstract: A high voltage semiconductor device is provided with a p layer which forms a main pn-junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is particularly effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

Abstract: Disclosed is a semiconductor device, comprising a substrate having a first region and a second region surrounding the first region, a MOS transistor formed in the first region, a first conductive layer formed in the first region and constituting the lower layer of a two-layered gate electrode of the MOS transistor, a second conductive layer for isolation, the second conductive layer being formed in the second region and having an upper surface whose level is lower than that of the upper surface of the first conductive layer, a first insulating layer formed between the first and second regions, a second insulating layer formed on the second conductive layer, and a third conductive layer formed over the first conductive layer and the second insulating layer and constituting the upper layer of the two-layered gate electrode of the MOS transistor.

Abstract: In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of operation of the device. A field plate structure (34, 34a, 34b, 34c) on an insulating layer (24) over the body portion (11) extends towards the outer periphery (14) to spread a depletion layer from the reverse-biased p-n junction (5) towards the outer periphery (14). The channel stopper (4) comprises concentrically doped stopper regions (41 to 44) with different doping concentrations and/or region widths and/or spacings, giving to the body portion (11) a non-uniform doping profile the doping of which, under the field plate structure (34, 34a, 34b, 34c), increases with distance (D) towards the outer periphery (14) to slow progressively the spread of the depletion layer under the field plate structure (34, 34a, 34b, 34c).

Abstract: The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.

Abstract: A manufacturing method of high voltage MOSFET includes a process forming the first and second conductive wells in a semiconductor substrate; process forming drift areas in the first and second conductive wells; process growing an isolation membrane on the substrate surface between the first and second conductive wells; process forming a gate insulation film; process forming a gate on the gate insulation film above the first and second conductive wells; process forming low concentration n- and p-type dopant areas in the drift areas of the parts adjacent to the gate; process forming buried diffusion areas in the first and second conductive wells; process forming source/drain having a body contact on a side on the buried diffusion areas in the first and second conductive wells; process forming an insulation film having a contact formed in such way that is exposed the surface of source/drain on the entire surface of the substrate including the gate and isolation membrane; process forming a metal film on the insul

Abstract: An improved edge termination scheme for semiconductor structures includes field-limiting rings (13, 14 and 15) having a fine-to-coarse incrementing scheme (18, 19 and 20) which is spatially additive assuring constancy against lateral junction variation. This spatially increasing scheme greatly enhances breakdown voltage characteristics. Additionally, redundant rings (14) are used to further guarantee insensitivity of the device to manufacturing variations. Reverse floating polysilicon flaps (28, 29 and 30) may be included to aid surface stability, when exposure to stray surface charges is anticipated. Additionally, this scheme provides for easy voltage scalability.

Abstract: An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area.

Abstract: The insulated gate bipolar transistor (IGBT) integrates the anti-excess voltage protection function and a drain voltage fixing function. When a voltage is applied across the drain electrode and the source electrode of the IGBT, a depletion zone propagates from a p-n junction between a p base layer and a n.sup.- drain layer toward inside of the n.sup.- drain layer. A critical electric field is also established, causing generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.- drain layer. Conduction exist between the drain electrode and the source electrode, at an applied voltage lower than a drain-source voltage at which the depletion region reaches a p.sup.+ drain layer through the n.sup.- drain layer, the applied voltage being equal to or lower than a critical voltage that causes generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.

Abstract: A high voltage semiconductor device is provided with a p layer which forms a main pn- junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is vey effective in improving the reliabilty of a high voltage control unit.

Abstract: A semiconductor device, which has a silicon body that includes at least one planar p-n junction that intersects a surface of the body, uses a multilayer arrangement that includes a first layer of thermally grown silicon dioxide, a second layer of Chemical-Vapor-Deposited (CVD) silicon nitride, a third layer of CVD oxygen-rich polysilicon, and a fourth layer of CVD silicon dioxide to passivate the junction. Common metallization contacts both the diffused region of the planar junction and the oxygen-rich polysilicon.

Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.