Abstract: A process, machine, manufacture, composition of matter, and improvement thereof, and method of making and method of using the same, as well as necessary intermediates, generally relating to the field of semiconductor devices, the structure of transistors, and the structure of compound semiconductor heterojunction bipolar transistors.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a first power line (such as Vdd), a second power line (such as Vss) and a bond pad of an integrated circuit respectively. The diode has an n electrode and a p electrode electrically connected to the first power line and the bond pad respectively.

Abstract: According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: A semiconductor device includes a power supply semiconductor chip that has a plurality of current passing electrodes and a plurality of control electrodes. Conductive plates are disposed on the current electrodes and the control electrodes, and extend to regions for external connections. The conductive plates also includes connecting regions that are suspended between the chip and the external connection regions and suppers vibration propagating to the chip. One conductive plate unit for the current passing electrodes and another conductive plate unit for the control electrodes are separately soldered on the corresponding electrodes. Alternatively, only one unit may be soldered on the semiconductor chip, and portions of the unit may be removed to fabricate the device. Because of the absence of wire-bonding steps, the semiconductor chip does not receive impact of wire-bonding during the manufacturing process.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of the bandgap reference circuitry.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: Formed on the surface of an n-type semiconductor layer (21) taken as a collector region is a base region (22) consisting of a p-type region, and formed in the p-type region is an emitter region (23) consisting of an n+-type region. Further, provided in the base region is a base electrode connecting portion (24) consisting of an n+-type region, and a base electrode (26) is connected to the surface of the base electrode connecting portion, and an emitter electrode (27) and a collector electrode (28) are provided and connected electrically to the emitter region and the collector region (21), respectively. As a result, a semiconductor device is obtained which has the transistor in which the reduction in power consumption with a high withstand voltage can be achieved, and the fast switching speed is possible and the large current is obtained. Further a voltage-drive type bipolar transistor such as a digital transistor is obtained which is small in load capacity while establishing a desired drive voltage.

Abstract: In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.

Abstract: Subcollector layers or emitter layers constituting a bipolar transistor having different thicknesses form a two-layered structure. A resistor layer is formed at the same as one of the subcollector layers or one of the emitter layers, from the same material as that of the subcollector layer or emitter layer. A resistor is formed by the resistor layer made of the same material as that of the subcollector layer or emitter layer. A resistor with a desired resistance can be integrally built into a semiconductor device without adversely affecting the characteristics of a bipolar transistor.

Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into the silicon layer from the free surface thereof, the base region being doped with impurities of a second conduction type, an emitter region extending into the base region from the free surface thereof, the emitter region being heavily doped with impurities of the first conduction type, and at least one collector region extending into the silicon layer from the free surface thereof at a lateral distance from the base region, the collector region being doped with impurities of the first conduction type, a floating collector region is provided in the silicon layer between the insulating layer and the base region at a distance from the base region.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.