Abstract: A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.

Abstract: A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and reduces the interlayer capacitance of the device. The semiconductor device has a semiconductor substrate including a MOS device, a plurality of wiring regions formed on the semiconductor substrate, and a protective insulation film formed on the top layer of the wiring regions. The protective insulation film includes a first silicon oxide film, a second silicon oxide film formed on the first silicon oxide film, and a silicon nitride film composing the top layer.

Abstract: Within a method for forming a halogen doped glass layer, such as a fluorosilicate glass (FSG) layer, there is first provided a substrate. There is then formed over the substrate a first halogen doped glass layer. There is then formed upon the first halogen doped glass layer a barrier layer. There is then formed upon the barrier layer a second halogen doped glass layer. Finally, there is then planarized the second halogen doped glass layer, while not penetrating the barrier layer, to form a planarized halogen doped glass layer.

Abstract: The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development.

Abstract: A method of manufacturing a semiconductor device which starts with a semiconductor wafer (1) which is provided with a layer of semiconductor material (4) lying on an insulating layer (3) at a first side (2). Semiconductor elements (5) and conductor tracks (14) are formed on this first side (2) of the semiconductor wafer (1). Then the semiconductor wafer (1) is fastened with this first side (2) to a support wafer (15), and material (18) is removed from the semiconductor wafer (1) from its other, second side (17) until the insulating layer (3) has been exposed. The method starts with a semiconductor wafer (1) whose insulating layer (3) is an insulating as well as a passivating layer. The semiconductor device must be provided with a usual passivating layer after its manufacture in order to protect it against moisture and other influences. In the method described here, such a passivating layer is present already before the manufacture of the semiconductor device starts.

Abstract: In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.

Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.

Abstract: A structure of a memory cell in a memory device is taking an interface between a silicon nitride layer and a oxide layer. The memory cell includes: a polysilicon layer on a substrate, a silicon nitride layer on the polysilicon layer, an oxide layer on the silicon nitride layer, and a conductor layer on the oxide layer. The order of forming the silicon nitride layer and the oxide layer can be reversed either for another alternative structure of the memory cell.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A pair of source/drain regions are formed on a semiconductor substrate at a predetermined interval. A gate insulator film is formed on the semiconductor substrate between the source/drain regions of the pair. A gate electrode is formed on the gate insulator film. A film for covering the gate electrode and the source/drain regions has a low permeability against water and a hydroxide group, and has a thickness greater than 3 nm and less than 5 nm.

Abstract: In an active area on a semiconductor substrate is formed a MOS transistor including a gate insulating film, gate electrode, an insulating film formed on the entire surface of the substrate, a conductive side wall formed on the side surfaces of the gate electrode with the insulating film interposed therebetween, low concentration source/drain regions and high concentration source/drain regions. The high concentration drain region and the conductive side wall are electrically conducting to each other via a second interconnection within a second contact hole. In the usage of the MOS transistor, the conductive side wall is at the same potential as the drain voltage, thereby suppressing the degradation due to a hot carrier. In addition, since there is no need to provide an alignment margin between the second contact hole and the gate electrode, the area of the drain region is decreased.

Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Abstract: A semiconductor device has a memory cell area which contains a component having a height and a peripheral circuit area free of a component having a height. The first area includes a interlayer insulating film comprising a first interlayer film as an uppermost insulating film. The second area includes an interlayer insulating film comprising the first interlayer film and a second interlayer film disposed directly on the first interlayer film and having a chemical mechanical polishing rate greater than the first interlayer film. The interlayer insulating film in the memory cell area has a surface higher than the interlayer insulating film in the peripheral circuit area.

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: Methods for depositing a nitride layer on a surface of an integrated circuit wafer for protecting against over etching during subsequent etching of overlying layers. A first nitride deposition method utilizes a chemical vapor deposition process having a variable ammonia flow rate. The ammonia flow rate is decreased during the chemical vapor deposition process. A second nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of an oxygen/argon plasma treatment to the surface of the nitride layer in a reactive ion etching process. A third nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of a nitrous oxide plasma treatment to the surface of the nitride layer in a chemical vapor deposition chamber.

Abstract: A moisture impervious film 24 such as silicon nitride is formed under an interlayer insulating film, covering the active region of an IC chip. The interlayer insulating film is formed, for example, by lamination of a silicon oxide film, a spin-on-glass (SOG) film, and another silicon oxide film. Moisture (H.sub.2 O) is intercepted by the moisture impervious film and does not reach the active region. It is possible to avoid the conductivity type inversion at the surface of a p-type well region in the active region and to suppress the corrosion of wiring layers, improving the reliability of the IC chip. The moisture impervious film is not limited to be formed at the layer under the silicon oxide film, but it is sufficient only if the film is formed at the layer under the SOG film.

Abstract: The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58.

Abstract: A structure for a semiconductor device includes a plurality of memory cell areas, a multilayer interconnection structure including an interfacial insulating film and connecting the plurality of memory cell areas, the multilayer interconnection structure being insulated and planarized by the interfacial insulating film, and peripheral circuits adjacent to the plurality of memory cell areas, the peripheral circuits intersecting at a portion, wherein the multilayer interconnection structure includes an inflow-preventing layer for preventing an inflow of the interfacial insulating film at the portion where the peripheral circuits intersect.

Abstract: A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E . . . (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.

Abstract: A semiconductor device comprises a lower conductive layer formed on a semiconductor substrate, a first insulation film layer formed at least on side faces of the lower conductive layer, a second insulation film layer formed around the lower conductive layer on which the first insulation film layer has been formed, a contact hole formed on the second insulation film layer in the vicinity of a side face of the lower conductive layer, and an upper conductive layer formed in the contact hole and over the second insulation film. The first insulation film layer is of a three-film structure comprising a first oxide film, a nitride film and a second oxide film.

Abstract: An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device areas, is described. A first insulating layer is formed over portions of the substrate. A gate insulating layer is formed surrounding the first insulating layer. The first ring surrounds a fuse area--including the area where the fuse will be cut by a laser or burned by a current. A first dielectric layer is formed over the substrate surface. A first passivation layer is then formed over the first insulating layer. A first opening is formed through the first passivation layer and first dielectric layer over the first ring. A fuse is formed over the first passivation layer over the fuse area and a second ring of water impervious material is formed on the first ring through the first opening. The first and second rings form a moisture impervious seal.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Abstract: A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

Abstract: A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.

Abstract: Metal wires are formed side by side over a semiconductor substrate, with an interlayer insulating film interposed between the metal interconnections and the semiconductor substrate. The metal interconnections are covered with a passivation film composed of a lower silicon oxide film and an upper silicon nitride film. The silicon oxide film is deposited so that the maximum thickness of the portions of the silicon oxide film on the side faces of the metal interconnections is less than half of the minimum space between the metal interconnections. The silicon nitride film is deposited so as to be interposed between the portions of the silicon oxide film on the side faces of the adjacent metal interconnections.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: According to this invention, after a semiconductor nitride film is formed on the entire surface of a semiconductor memory device, the semiconductor nitride film on a memory cell portion is removed. After a semiconductor oxide-based film is formed as an interlayer insulator on the entire surface of the semiconductor memory device, the semiconductor oxide-based film on a peripheral circuit portion is removed using the semiconductor nitride film as a stopper. For this reason, a shallow contact hole is formed in the peripheral circuit portion, and highly reliable wiring can be obtained. In addition, since hydrogen can be supplied to a surface of a semiconductor substrate in the memory cell portion by hydrogen annealing, an interface state on the surface can be eliminated, and the data retention characteristics of the memory cells can be improved.

Abstract: A multilayer insulating film of a semiconductor device, where the distributed quantity of carbon or fluorine is maximized at the interface between insulating films. The concentration of carbon present at the interface is 1.times.10.sup.20 atoms/cm.sup.3 or more.

Abstract: An integrated circuit capacitor is formed on a semiconductor substrate by forming an insulating layer over the substrate, forming a sacrificial layer on the insulating layer and patterning it. A first polysilicon layer is formed in an opening in the sacrificial layer which is then removed. A second insulating layer is formed over the conducting layer and the exposed substrate. A second polysilicon layer, and a third insulating layer are formed. A mask is formed over the first polysilicon layer. A polysilicon oxidation product is formed in place of the second polysilicon layer away from the first polysilicon conducting structure. A mask is formed over the surface of the device, etching through the mask to the substrate and the second polysilicon layer. Metallization is deposited onto the surface of the mask and into the openings therein. The polysilicon layers are conductive.

Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.

Abstract: There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.

Abstract: A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A semiconductor device having a superior step coverage of a layer formed inside or near a contact-hole is provided. An intermediate conductive layer is formed through an insulating layer on a lower conductive layer on a semiconductor substrate, and first, second and third inter-layer insulating layers are formed on the intermediate conductive layer. The third inter-layer insulating layer is selectively removed by an isotropic wet etching method thereby to form a through-hole extended to the second inter-layer insulating layer and having a large opening area. In performing this, the second inter-layer insulating layer acts to restrict the removal of the third inter-layer insulating layer in the thickness direction. Next, the first and second inter-layer insulating layers are selectively removed by an anisotropic dry etching method thereby to form a through-hole having a small opening area. The through-hole having a large opening area and the through-hole having a small opening area form a contact-hole.

Abstract: An electrically programmable read only memory device store data bits in the form of electric charges accumulated in floating gate electrodes of the memory cells, and a spin-on glass film is incorporated in an inter-level insulating film structure over the memory cells so as to create a smooth surface for wirings, wherein a silicon oxynitride film is inserted between the floating gate electrodes and the spin-on-glass film for preventing the accumulated electric charges from undesirable ion-containing water diffused from the spin-on-glass film.