Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.

Abstract: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2).

Abstract: A method of manufacturing a magnetic memory device includes forming an insulation layer on a substrate, forming a lower electrode on the insulation layer, forming a magneto-resistive film on an upper surface of the lower electrode, the magneto-resistive film including an insulation barrier layer and a plurality of magnetic films stacked on both sides of the insulation barrier layer, stacking a mask layer on the magneto-resistive film, performing ion etching on the magneto-resistive film, using the mask layer as a mask, thereby forming a magneto-resistive element, forming an insulation film on upper surfaces of the mask, the magneto-resistive element and the lower electrode, and etching the insulation film with an ion beam such that a side surface of the magneto-resistive element is exposed.

Abstract: In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: A substrate for mounting a device is disclosed. The substrate includes at least one transition for providing an RF connection to a lead of the device, the lead extending from a device input to an otherwise free end. The transition comprises two spaced apart electrically coupled members, the first member occupying at least the same area on a top surface of the substrate as the device lead to which it is to connect, and the second member lying in register with the first member. The transition comprises an input, which is located at the end of the second member which is nearest the free end of the device lead and an output which is located at the opposite end of the first member and which is in register with the device input. The electrical characteristics of the transition are such that the electrical length from the input of the transition to the output of the transition is approximately equal to one half of a wavelength over a given operating frequency band of the device.

Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Abstract: Apparatus for suppressing noise and electromagnetic coupling in the printed circuit board of an electronic device includes an upper conductive plate and an array of conductive coplanar patches positioned a distance t2 from the upper conductive plate. The distance t2 is chosen to optimize capacitance between the conductive coplanar patches and the upper conductive plate for suppression of noise or electromagnetic coupling. The apparatus further includes a lower conductive plate a distance t1 from the array of conductive coplanar patches and conductive rods extending from respective patches to the lower conductive plate.

Abstract: The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.

Abstract: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer. A third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure. Thus, the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path, and the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.

Abstract: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle are configured to provide continuity of ground between the circuit board and a chip mounted to the paddle.

Abstract: A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.

Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device has a probing pad formed on a chip. The probing pad is connected to an output pad and an internal circuit though a fuse. After an electrical testing of the chip by the probing pad, the fuse is cut by a laser beam. Therefore, the probing pad is disconnected from the output pad and the internal circuit. The output pad is connected to an output lead of a package, which is encapsulating the chip. According to the device and the fabrication methods thereof, performance of the device can be enhanced by a low parasitic capacitance and a low parasitic resistance.

Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulation film formed above the semiconductor substrate, a fuse formed on or in the interlayer insulation film, and a wiring layer formed in a portion of the interlayer insulation film, which is under the fuse, the wiring layer being isolated from the fuse and having a width smaller than the fuse.

Abstract: A fuse circuit according to the present invention includes first and second fuses, each of which has a first end and a second end. The first and second ends of the first fuse are connected in a straight line. The first end of the second fuse is spaced by a first interval from the first end of the first fuse, and the second end thereof is spaced by a second interval from the second end of the first fuse. The first ends of the first and second fuses have the same widths as those of the second ends thereof. Alternatively, the first ends of the first and second fuses have narrower widths that those of the second ends thereof.

Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.

Abstract: A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

Abstract: By providing an end portion of a radiation plate located on and near an end portion of an insulator sheet, to which a lead frame extends, at a position away from the end portion of the insulator sheet inside of the insulator sheet in a plane direction of the insulator sheet, it is possible to secure a creeping distance between the lead frame and the radiation plate without decreasing a lead frame area on which components can be actually mounted.

Abstract: A method to protect a low-K IMD layer underlying a fuse link during a fuse blowing process including a guarded fuse and method for forming the same including forming a fuse portion comprising two metal fuse interconnect structures and a guard ring comprising a metal interconnect structure surrounding the fuse portion in an uppermost IMD layer comprising a dielectric constant of less than about 3.2; forming a protective metal portion electrically isolated in the uppermost IMD layer to cover at least a portion of an area extending between the fuse portions; forming at least one overlying dielectric insulating layer over the uppermost layer to include extended portions of the fuse portion and the guard ring; and, forming a metal fuse link portion to electrically interconnect the fuse portion wherein the fuse portion overlies at least a portion of the protective metal portion.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A semiconductor device includes a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: A semiconductor integrated circuit device has a semiconductor integrated circuit chip, a package enclosing the chip, and a plurality of conductors connecting the bonding pads of the chip to the leads of the package. The chip has an internal circuit, a plurality of bonding pads having signal paths formed between themselves and the internal circuit, and a switching circuit provided in a predetermined signal path so as to perform a switching operation to allow the internal circuit to be connected selectively to one of different bonding pads. The switching circuit is fed with an external signal to perform its switching operation in such a way as to prevent the signals passing through mutually adjacent conductors from affecting each other.

Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. The package may also substantially encapsulate the lead frame, while exposing the die paddle and the input/output leads.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlayer insulating film (8), closer to outside than the copper interconnect lines (2). A silicon nitride film (9) is provided on the via-shaped copper interconnect lines (2), on the copper interconnect line (6) of the shield ring (5), and on the interlayer insulating film (8). Provided on the silicon nitride film (9) is a silicon oxide film (10) which holds therein a fuse line (3) for connecting different ones of copper interconnect lines (2). The silicon oxide film (10) is also provided on the upper surfaces of the fuse line (3) and the aluminum interconnect line (7). A silicon nitride film (11) is provided on the silicon oxide film (10). The silicon nitride film (11) defined over the fuse line (3) is removed, thereby creating an opening (4).

Abstract: A semiconductor device includes a semiconductor die having patterned circuitry, a plurality of terminals coupled to the die, and an indication providing signal noise information of at least one of the terminals.

Abstract: A fuse structure for a semiconductor device on a substrate includes a fuse having an electrically conductive fuse line of a standard fuse length formed in an electrically conductive layer disposed over the substrate, and a pair of electrically conductive, inwardly bent interconnects formed in a first plurality of electrically conductive layers disposed over the substrate, below the electrically conductive layer in which the fuse line is formed. The inwardly bent interconnects couple the fuse line to a circuit area of the substrate disposed under the fuse line. The fuse structure may further include a protective guard ring formed around the fuse. The guard ring includes a second plurality of electrically conductive interconnects.

Abstract: A plurality of lead frames is supplied in lead frame by lead frame sequence. A curable adhesive, preferably a 505 Epoxy, is applied to one surface of each lead frame as it indexes through an application device. An attaching device attaches a device to each lead frame with the adhesive by holding the device in place to cure for a preselected period of time of about one second. Later, the lead frames have their edges trimmed and then are separated into separate lead frames.

Abstract: A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a potential fixed at the ground potential, at least one crossing portion in which the wiring layers mutually cross, with insulating interlayers provided therebetween, and at least one separation electrode being selectively provided on one of the insulating interlayers, the at least one separation electrode having a potential fixed at the ground potential. Accordingly, in the high frequency semiconductor device, electrical interference between two crossing wiring layer is prevented and transmission loss is suppressed.

Abstract: The present invention relates to a microwave electronic device (1) comprising a metal enclosure (2) having a bottom (21) and a lid (23) and containing an electronic circuit board (3) disposed substantially parallel to said bottom and to said lid, said circuit board having: conductive bottom and top grounding layers (41, 42) respectively disposed on bottom and top faces (31, 32) of the circuit board, and perforations (7a) transverse to said faces of the circuit board and delimited by conductive walls (71) for electrically interconnecting said layers (41, 42). At least some of said walls (71) are electrically connected to the lid of the enclosure by conductive grounding members (8a). Each conductive member (8a) has a metal blade covered with a material (13, 13?) for absorbing microwaves.

Abstract: An IC chip has externally and selectively cuttable members F1-F3, which can be cut, or cut open, at more than one cuttable points C1 and C2. So long as at least one of the multiple cuttable points C1 and C2 remains cut open, the cuttable member works as a cut member. Thus, a cut member has an exceedingly small probability that it is short-circuited by particles in an ACF or by dust.

Abstract: A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.

Abstract: An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode. When a short occurs, the single pixel may be separated from the circuit by the fuse, avoiding the possibility that an entire row of pixels may be adversely affected by the short associated with one single pixel along a row.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. A plastic mold compound substantially encases the lead frame, while exposing the die paddle and the input/output leads. Incorporating the transmission line into the lead-frame avoids having to place the matching network outside of the integrated circuit package. That is, etching the lead frame to provide the transmission line, and placing components (e.g., capacitors, inductors, etc.

Abstract: Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are different from each other in a direction in which the fuse electrodes extend. Since the cutting positions on the adjacent fuse electrodes are different from each other, the adjacent fuse electrodes are prevented from being short-circuited by fragments of components thereof that are scattered when the laser beam is applied to cut off the fuse electrodes.

Abstract: A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.