Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Abstract: The application describes an antenna packaging module for a semiconductor chip and a method for making it. The antenna packaging module comprises a redistribution layer, an antenna structure, a semiconductor chip, a metal bump, a third packaging layer and a packaging antenna connector. The antenna structure comprises a connector opening, a first antenna structure and a second antenna structure stacked on the second surface of the redistribution layer. The packaging antenna connector is disposed in the connector opening, and is electrically connected to the redistribution layer. Electrical interconnection of packaging an antenna connector in a connector opening in the packaging layer, the antenna signal loss is reduced, and the overall e advantage of WLP AiP is further improved.

Abstract: A heat sink is described for cooling an electrical component. The heat sink has heat dissipating structures connected to a base. The base is attached to a connector which makes contact with a heat transfer contact of the electrical component. The electrical component may be a power supply bus which supplies electrical current to a series of circuit breakers.

Abstract: Removing device including: a heat exchanger that is mounted on a platen so that the exchanger lies above and a distance away from an electronic component; a chassis that lies between the electronic component and the platen, and device for fastening the chassis to the platen or to the electronic board; a rigid heat sink that is mounted on the chassis in order to slide perpendicularly to the electronic board and that has a first end making contact with the component and a second end in abutment against a thermally conductive layer that is fastened to the platen in order to elastically return the rigid heat sink into abutment against the electronic component whatever the thickness of the electronic component. Electronic equipment having such a removing device.

Abstract: A pressure contact-type semiconductor module includes a plurality of semiconductor units disposed side-by-side, each of the semiconductor units including: a semiconductor device substrate; a first electrode formed below the semiconductor device substrate, a second electrode formed above the semiconductor device substrate, an electrode plate electrically connected to the second electrode; and a pressure contact adjustment member screwed into the electrode plate, the pressure contact adjustment member having a top surface as a pressure contact-receiving surface to which a lead-out electrode plate that is common to the plurality of semiconductor units is to be pressure-contacted, levels of the respective top surfaces of the pressure contact adjustment members in the plurality of semiconductor units being adjustable to match a reference pressure contact plane so that contact pressures in the respective top surfaces applied by the lead-out electrode plate are substantially the same among the semiconductor units.

Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

Abstract: In one example an electronic device comprises at least heat generating component, a heat spreader positioned proximate the at least one heat generating component and a passive radiator cooling device, comprising an enclosure, an active speaker positioned at least partially within the enclosure, and a passive audio radiator positioned at least partially within the enclosure. Other examples may be described.

Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.

Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.

Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.

Abstract: The present invention relates to an electronic device for switching currents and a method for producing such a device that is reliable and durable. Such an electronic device comprises a power semiconductor that can be actuated for switching between at least two states; a substrate having thermomechanical properties compatible with the power semiconductor on which the power semiconductor is disposed on one side; a bus bar disposed on the other side of the substrate for conducting the current, wherein the substrate and the bus bar are coupled to each other such that a heat-conductive connection is provided so that heat can be dissipated from the power semiconductor to the bus bar.

Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.

Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.

Abstract: An electrical and/or electronic device including: an electrical and/or electronic component; two layers of material forming front and back faces of the device and between which the electrical and/or electronic component is encapsulated, the component including at least two opposite faces placed facing the two layers of material; an electrical contact element placed in contact with one of the faces of the electrical and/or electronic component; an element based on at least one elastic material placed between one of the two layers of material and the electrical contact element, forming a first layer of elastic material covering the one of the two layers of material; and a second layer based on at least one elastic material with an elastic stiffness less than the stiffness of the elastic material in the first layer, placed in contact with the first layer of elastic material.

Abstract: An LED assembly including a heat sink, a surface treatment dielectric layer, an electrically conductive layer, a thermally conductive layer and an LED chip. The surface treatment dielectric layer is disposed on an upper surface of the heat sink and defines at least one first through hole to expose a portion of the upper surface. The electrically conductive layer is formed on the surface treatment dielectric layer, includes a plurality of electrical traces and defines at least one second through hole corresponding to the first through hole. The thermally conductive layer is formed in the first and the second through holes and directly contacted with a portion of the upper surface exposed from the overlapped region of the first through hole and the second through hole. The LED chip includes a plurality of electrodes electrically connected to the electrical traces and is directly contacted with the thermally conductive layer.

Abstract: An object is to provide a thin and small semiconductor device that has high reliability and high resistance to external stress and electrostatic discharge. Another object is to manufacture a semiconductor device with high yield while shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process. A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown (malfunction of the circuit or damage to a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge. By providing an antenna on the external side of the conductive shield, a sufficient communication capability is secured. With the use of a pair of insulators which sandwich the semiconductor integrated circuit, a thin and small semiconductor device that has resistance properties and high reliability can be provided.

Abstract: An apparatus having a substrate, an LED light source attached to the substrate, an electrical connector attached to the substrate and electrically connected to the LED light source, a potting material on the substrate and covering at least a portion of the electrical connector; and a barrier separating the potting material from the LED light source, the barrier having a height that exceeds the thickness of the potting material on the substrate.

Abstract: A wafer assembly comprises a wafer having a MEMS layer formed on a frontside and a polymer coating covering the MEMS layer. A holding means is releasably attached to the polymer coating so that the wafer assembly facilitates performance of backside operations on a backside of the wafer. The polymer coating is comprised of a polymerized siloxane.

Abstract: A memory heat sink device having an enlarged heat dissipating area is provided. The memory heat sink device includes two cooling fins that are respectively attached to a front side and a back side of a memory. Raised dots are protruded from a front (or back) side of the cooling fin attached to the front (or back) side of the memory. Each of the raised dots on the cooling fin has at least one sectional area and at least one connection portion. Thus, the heat sink area of the cooling fin increases and heat generated by the memory is easily dissipated by the sectional area through thermal convection.

Abstract: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer.

Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.

Abstract: A memory module assembly (100) includes a memory card (200) having a right side surface (240) and a left side surface (220), a heat sink (400) and a heat pipe (500). The heat sink includes a base member (420) attached to the left side surface of the memory card and a shell (440) attached to the right side surface of the memory card and coupled to the base member. The base member includes a substrate portion (422) attached to the left side surface of the memory card and a support portion (424) extended from the substrate portion and supported on a top edge of the memory card. The heat pipe includes an evaporator (520) in thermal engagement with one of the shell and the substrate portion and a condenser (540) in thermal engagement with the support portion.

Abstract: A bonded body consisting of a ceramic member and a metal composite member of which bonding layer is less likely to be eroded by plasma is provided. The bonded body comprises the ceramic member that has two opposing main surfaces with a first metal layer provided on one of the main surfaces, the metal composite member that has two opposing main surfaces with a second metal layer provided on one of the main surfaces, and a brazing material layer that joins the first metal layer and the second metal layer, wherein the brazing material layer has an outer circumferential surface that has a depression formed therein at middle position in the direction of thickness thereof, with the depression having width at least one third the thickness of the brazing material layer.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Abstract: An electronic component includes an electronic element, a conductive first base portion, a conductive second base portion, an insulator and a terminal. An electronic element is to be mounted on the electronic element mounting portion. The electronic element mounting portion is mounted on the first base portion. The insulator insulates the first base portion from the second base portion and couples the first base portion to the second base portion. The terminal is provided on the first base portion and is insulated from the first base portion.

Abstract: In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped and is made of glass, of a seal cap having a structure in which a cavity is constituted by the protruded bonding portion, is anodically bonded to a bonding portion of the silicon circuit substrate, thus, the electronic parts is hermetically sealed in the cavity of the sealing cap.

Abstract: A high frequency device module of an embodiment of a current invention includes: an insulation substrate in which electrodes are provided on the front surface thereof and a grounding substrate is provided on the rear surface thereof; a high frequency device provided on the insulation substrate with a terminal of the device connected to the electrodes; potting material for covering the high frequency device; and a metallic layer provided on the potting material and connected to the grounding substrate.

Abstract: Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin (sealing resin) provided so as to cover the semiconductor chip and the film. As a result, deterioration in contact property with the sealing resin is suppressed and a high frequency characteristic can be enhanced.

Abstract: Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor and a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one microlens in the array includes a plurality of mutually adhered layers of cured optically transmissive material.

Abstract: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane) mounted on a thin support substrate and interfaced with a die. Thermally conductive via interconnects extending through the substrate conduct heat generated by the die from the conductive plane to conductive balls mounted on traces on the opposing side of the substrate. In another embodiment, the semiconductor devices comprises a thick thermally conductive plane (e.g., copper foil) sandwiched between insulative layers, with signal planes (e.g., traces, bonding pads) disposed on the insulative layers, a die mounted on a first signal plane, and solder balls mounted on bonding pads of a second signal plane.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer.

Abstract: An electronics unit includes a low multi-point metallic mount on which an insulating layer is arranged. A conductor track system is arranged on the insulating layer and electronic power components are arranged on the conductor track system. The insulating layer is a sintered electrically insulating polymer layer on which the conductor track system, which comprises a sintered glass frit with a noble metal filling, is arranged.

Abstract: A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.

Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

Abstract: A thermal transfer material is described herein that includes: a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material, and at least one solder material, wherein the solder material is directly deposited onto the bottom surface of the heat spreader component. Methods of forming layered thermal interface materials and thermal transfer materials include: a) providing a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material; b) providing at least one solder material, wherein the solder material is directly deposited onto the bottom surface of the heat spreader component; and c) depositing the at least one solder material onto the bottom surface of the heat spreader component.

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract: A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at least one semiconductor die and at least partially cured substantially as a whole. Methods of forming conductive elements such as traces, vias, and bond pads are also disclosed. More specifically, forming at least one organometallic layer to a substrate surface and selectively heating at least a portion thereof is disclosed. Also, forming a layer of conductive photopolymer over at least a portion of a surface of a substrate and removing at least a portion thereof is disclosed. A microlens having a plurality of mutually adhered layers of cured, optically transmissive material, methods of forming same, and systems so equipped are disclosed.

Abstract: A tool is used to hold an array of wafer scale protective caps and place the array onto a semiconductor wafer. The tool comprises a first tool half made from a semiconductor which has a coefficient of thermal expansion which is about the same as that of the wafer. The first tool half has surface features for molding and retaining the array. The caps have central areas surrounded by sidewalls.

Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.

Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.

Abstract: A system for chip packaging includes an adamantoid packaging composition. The adamantoid composition ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In an embodiment, the system includes a packaging composition that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a chip package that uses an adamantoid packaging composition.

Abstract: To offer a semiconductor light-emitting device capable of preventing a short circuit failure caused by adhesion of the solder, change of a beam shape, and decrease of a beam output. A semiconductor laser device 1 is manufactured by overlaying a laser chip having a p-side electrode and a n-side electrode in a crystalline substrate and a mounting plate having a first solder film and a second solder film in a supporting body. The laser chip has a level difference A such that the p-side electrode is projected beyond the n-side electrode. The mounting plate has a level difference B such that the first solder film is projected beyond the second solder film. The level difference B of the mounting plate is determined as higher than the level difference A of the laser chip. Therefore, when the mounting plate is overlaid to the laser chip, first, the n-side electrode contacts with the second solder film, and then, the p-side electrode contacts the first solder film.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; at least one layer of a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less, an entire layer of the first insulating film being separated at least near four corners of the semiconductor substrate by a lacking portion that extends along the four corners; and a second insulating film covering a side face of the entire layer of the first insulating film in the lacking portion on a center side of the semiconductor substrate and having a relative dielectric constant of over 3.8.

Abstract: A semiconductor device and package has a heat spreader directly disposed on the reverse surface of the semiconductor device. This heat spreader includes a diamond layer or a layer containing diamond and ceramics such as silicon carbide and aluminum nitride. The heat spreader is directly formed on a substrate for the semiconductor device. In particular, the heat spreader is composed of a diamond layer and one or two metal or ceramic members, which are bonded to the diamond layer with one or two polymer adhesive layers. This diamond layer has a fiber structure across the thickness or a microcrystalline structure. Cilia are formed on a surface of the diamond layer facing the one or two metal or ceramic members.

Abstract: A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.

Abstract: A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.