Devices Held In Place By Clamping Patents (Class 257/726)
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Patent number: 7977698Abstract: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical connections are run to the edges of the substrate and end in electrical contacts positioned thereat. The substrate is then connected to the scrambler package by a series of electrical and mechanical connections to form the LED package. The electrical contacts which are part of the LED package extend from the LED package so as to enable electrical contact with a separate controller substrate.Type: GrantFiled: March 18, 2005Date of Patent: July 12, 2011Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventors: Elizabeth Fung Ching Ling, Chia Chee Wai, Ng Joh Joh, Koay Hui Peng
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Patent number: 7960828Abstract: The carrier frame relating to the present invention comprises a base layer member, a frame layer member, and a positioning layer member having multiple openings for storing electronic components. A spring layer member is mounted in a hollow part surrounded by the frame layer member between the positioning layer member and the base layer member. At each opening of the spring layer member, a small spring providing an elastic force for fastening the electronic components between an edge of the corresponding opening of the positioning layer member and the small spring is formed integrally with the spring layer member. At one end in the longitudinal direction of the spring layer member, a large spring providing an elastic force along the longitudinal direction by being in contact with an inner surface of the frame layer member in the mounted state is formed integrally with the spring layer member.Type: GrantFiled: October 6, 2008Date of Patent: June 14, 2011Assignee: Panasonic CorporationInventors: Toshihiko Satou, Kazuhiko Takahashi, Kazuto Nishida, Satoru Waga
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Patent number: 7944042Abstract: A semiconductor device includes an outer resin case having a peripheral wall and terminal mounting holes formed in the peripheral wall, and a layer assembly provided in the outer resin case. The layer assembly includes a semiconductor chip, an insulating circuit board on which the semiconductor chip is mounted, and a heat-dissipating metal base. External terminals having leg portions are arranged in mounting holes of the peripheral wall, and are press-fitted into the terminal-mounting holes. Bonding wires connect the terminal leg portions and a conductive pattern of the insulating circuit board or the semiconductor chip.Type: GrantFiled: February 12, 2008Date of Patent: May 17, 2011Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Katsuhiko Yoshihara, Rikihiro Maruyama, Masaaki Chino, Eiji Mochizuki, Motokiyo Yokoyama, Tatsuo Nishizawa, Tomonobu Sugiyama
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Patent number: 7936062Abstract: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.Type: GrantFiled: January 19, 2007Date of Patent: May 3, 2011Assignee: Tessera Technologies Ireland LimitedInventors: Giles Humpston, Michael J. Nystrom, Vage Oganesian, Yulia Aksenton, Osher Avsian, Robert Burtzlaff, Avi Dayan, Andrey Grinman, Felix Hazanovich, Ilya Hecht, Charles Rosenstein, David Ovrutsky, Mitchell Hayes Reifel
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Patent number: 7902657Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.Type: GrantFiled: August 28, 2007Date of Patent: March 8, 2011Assignee: Fairchild Semiconductor CorporationInventor: Jocel P. Gomez
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Apparatus for mounting a module and enabling heat conduction from the module to the mounting surface
Patent number: 7864534Abstract: An electronics enclosure is provided. The electronics enclosure includes a heat dissipating body comprising: a heat conducting surface, a first flange adjacent to the heat conducting surface, and a first part of a latch mechanism adjacent to the heat conducting surface. The first part of the latch mechanism is adjacent an edge of the heat conducting surface opposite to the first flange, such that a portion of the heat conducting surface is between the first flange and the first part of the latch mechanism. The electronics enclosure also includes a plurality of electronic modules configured to mount to the heat dissipating body.Type: GrantFiled: June 11, 2008Date of Patent: January 4, 2011Assignee: ADC Telecommunications, Inc.Inventors: Michael J. Wayman, Michael J. Nelson -
Patent number: 7845074Abstract: The method for manufacturing an electronic parts module includes an adhesive layer forming process forming an adhesive layer including solder particles on the circuit forming surface in range covering at least the first land part and the second land part; a passive element mounting process positioning a terminal of the passive element on the first land part and sticking the passive element to the base wiring layer through the adhesive layer; an active element mounting process, after the passive element mounting process, positioning a terminal of the active element on the second land part and sticking the active element to the base wiring layer through the adhesive layer; a pressing process solidifying the adhesive layer and melting the solder particles by laminating and thermally pressing a thermosetting sheet onto the circuit forming surface so as to form the resin sealing layer.Type: GrantFiled: April 15, 2009Date of Patent: December 7, 2010Assignee: Panasonic CorporationInventors: Koji Motomura, Hideki Eifuku, Tadahiko Sakai
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Patent number: 7841081Abstract: The manufacturing method for an electronic parts module includes forming an adhesive layer including solder particles on the circuit forming surface in range covering at least the first and the second land parts, positioning a terminal of the active element on the second land part, sticking the active element to the base wiring layer through the adhesive layer by heating and pressing the active element onto the base wiring layer with a thermally pressing tool, and releasing the heating and pressing with the thermally pressing tool while the adhesive layer is semi-solidified, thereafter positioning a terminal of the passive element on the first land part and sticking the passive element to the base wiring layer through the adhesive layer, and solidifying the adhesive layer and melting the solder particles by laminating and thermally pressing a thermosetting sheet onto the circuit forming surface to form the resin sealing layer.Type: GrantFiled: April 15, 2009Date of Patent: November 30, 2010Assignee: Panasonic CorporationInventors: Koji Motomura, Hideki Eifuku, Tadahiko Sakai
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Patent number: 7838987Abstract: An electronic device comprises a semiconductor device having a package substrate with bumps. The semiconductor device is bonded to a mounting substrate by flip-chip bonding. A standoff member supports the package substrate on the mounting substrate with a predetermined standoff between the package substrate and the mounting substrate. The standoff member comprises a hole provided in the mounting substrate, an insertion portion provided to be contained in the hole, and a standoff portion provided to contact and support the package substrate such that the standoff portion has a height, equivalent to the predetermined standoff, on the mounting substrate and enables relative displacement of the package substrate to the mounting substrate.Type: GrantFiled: May 19, 2005Date of Patent: November 23, 2010Assignee: Fujitsu LimitedInventor: Tsuyoshi So
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Patent number: 7834444Abstract: An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.Type: GrantFiled: February 26, 2009Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Elie Awad, John Jay Maloney
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Patent number: 7821785Abstract: A baffle has a slot, with the slot positioned between first and second adjacent components when the baffle is installed above the components. A pair of heatsinks are inserted into the slot, with at least one heatsink having a heat dissipating portion that remains above the slot after insertion into the slot. A spring is inserted into the slot between the pair of heatsinks.Type: GrantFiled: April 20, 2009Date of Patent: October 26, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventor: Matthew D. Neumann
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Patent number: 7800222Abstract: A semiconductor module comprises at least one semiconductor chip having at least one semiconductor switch. The at least one semiconductor chip is arranged on a carrier substrate. At least one driver component drives the at least one semiconductor switch. The at least one driver component is arranged on a circuit board. The at least one driver component has at least one input for receiving a control signal. The circuit board has a galvanic isolation in a signal path between the at least one driver component and the at least one semiconductor chip.Type: GrantFiled: November 29, 2007Date of Patent: September 21, 2010Assignee: Infineon Technologies AGInventors: Martin Schulz, Uwe Jansen
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Patent number: 7750486Abstract: A sensor includes: a first chip; a second chip disposed on the first chip through an adhesive member; and a stopper. The second chip is connected to the first chip through a bonding wire. The stopper limits a displacement of the second chip when the adhesive member is deformed. The stopper is disposed around the second chip. Since the displacement of the second chip is restricted, deformation of the bonding wire between the first and the second chips is also restricted.Type: GrantFiled: March 31, 2008Date of Patent: July 6, 2010Assignee: DENSO CORPORATIONInventor: Tameharu Ohta
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Patent number: 7705442Abstract: A contact device for use with a power semiconductor component in a power semiconductor module or a disc-type thyristor, the module or thyristor having a molded body with a first recess disposed above the component. The contact device makes electrical contact with the auxiliary connection of the component, and is disposed within a second recess in the module or thyristor. The contact device includes a spring having a pin-like extension at a first end thereof that faces the component and a metal molded body that is arranged at the opposite end thereof and has a first connecting device formed as a flat section of the metal molded body. The flat section is arranged generally parallel to the component, and has a second connecting device for connection to a connecting cable. The connecting device may also have a multipart insulating housing for holding the contact spring and the metal molded body.Type: GrantFiled: July 30, 2007Date of Patent: April 27, 2010Assignee: SEMIKRON Elektronik GmbH & Co. KGInventor: André Schlötterer
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Patent number: 7692293Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.Type: GrantFiled: December 17, 2004Date of Patent: April 6, 2010Assignee: Siemens AktiengesellschaftInventors: Walter Apfelbacher, Norbert Reichenbach, Johann Seitz
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Patent number: 7683469Abstract: A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base.Type: GrantFiled: May 30, 2008Date of Patent: March 23, 2010Assignee: Stats Chippac Ltd.Inventors: JiHoon Oh, KyuWon Lee, Jaehyun Lim, JongVin Park, SinJae Lee
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Patent number: 7679162Abstract: An integrated current sensor package includes an integrated circuit having a coil in a metal layer of the circuit. A wire is placed close enough to the coil such that the coil and the wire are inductively coupled with each other.Type: GrantFiled: December 19, 2005Date of Patent: March 16, 2010Assignee: Silicon Laboratories Inc.Inventors: Timothy J. Dupuis, John Pavelka
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Patent number: 7675166Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).Type: GrantFiled: May 11, 2005Date of Patent: March 9, 2010Assignee: Maxim Integrated Products, Inc.Inventors: Jeff Alan Gordon, Steven N. Hass, Hal Kurkowski, Scott Jones
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Patent number: 7663232Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.Type: GrantFiled: March 7, 2006Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventor: Thomas H. Kinsley
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Patent number: 7651308Abstract: A carrier for a semiconductor device includes a body having an opening formed therein to receive the semiconductor device and a pair of rollers to hold the semiconductor device between the rollers in the opening.Type: GrantFiled: June 5, 2008Date of Patent: January 26, 2010Assignee: Intel CorporationInventor: John D. Ruth
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Patent number: 7638814Abstract: Standard solderless connectors extend from a molded package body supporting at least one high power LED. The package includes a relatively large metal slug extending completely through the package. The LED is mounted over the top surface of the metal slug with an electrically insulating ceramic submount in-between the LED and metal slug. Electrodes on the submount are connected to the package connectors. Solderless clamping means, such as screw openings, are provided on the package for firmly clamping the package on a thermally conductive mounting board. The slug in the package thermally contacts the board to sink heat away from the LED. Fiducial structures (e,g., holes) in the package precisely position the package on corresponding fiducial structures on the board. Other packages are described that do not use a molded body.Type: GrantFiled: June 19, 2007Date of Patent: December 29, 2009Assignee: Philips Lumileds Lighting Company, LLCInventors: Franklin Wall, Jr., Peter Stormberg, Jeffrey Kmetec, Mina Farr, Li Zhang
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Patent number: 7622813Abstract: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes that vary when rotated 360°, such that the microstructures are positioned at a specific orientation in the receptacles.Type: GrantFiled: April 23, 2007Date of Patent: November 24, 2009Assignee: HRL Laboratories, LLCInventor: Peter D. Brewer
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Patent number: 7618896Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.Type: GrantFiled: April 24, 2006Date of Patent: November 17, 2009Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Venkat Iyer, Jonathan Klein
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Patent number: 7612446Abstract: A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottomType: GrantFiled: November 22, 2006Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Hien P. Dang, Vinod Kamath, Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha, Jung H. Yoon
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Patent number: 7606042Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.Type: GrantFiled: October 9, 2007Date of Patent: October 20, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Patent number: 7603769Abstract: Methods of coupling a surface mount device with a substrate such as a printed circuit, for example, are disclosed. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed there between, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.Type: GrantFiled: September 14, 2007Date of Patent: October 20, 2009Assignee: Intel CorporationInventor: My Jang
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Patent number: 7592688Abstract: A multi-chip semiconductor package that includes two power semiconductor devices arranged in a half-bridge configuration between two opposing circuit boards.Type: GrantFiled: January 16, 2007Date of Patent: September 22, 2009Assignee: International Rectifier CorporationInventor: Martin Standing
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Patent number: 7576429Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.Type: GrantFiled: February 28, 2006Date of Patent: August 18, 2009Assignee: Fairchild Semiconductor CorporationInventors: Ruben P. Madrid, Romel N. Manatad
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Patent number: 7539018Abstract: An electrical connector assembly is provided that includes a guide frame having an internal compartment configured to receive an electrical component. The guide frame extends a length between a plug end portion having a plug opening and a rear end portion opposite the plug end portion. The guide frame includes a first wall that extends between the rear end portion and the plug end portion. The first wall includes a heat sink retention area that is configured to receive a heat sink. The rear end portion includes a rear wall. A clip is configured to be mounted on the guide frame. The clip is configured to extend over and engage at least a portion of the heat sink when the heat sink is received by the heat sink retention area. The clip is configured to engage the rear wall of the guide frame and extend along at least a portion of the first wall of the guide frame.Type: GrantFiled: October 31, 2007Date of Patent: May 26, 2009Assignee: Tyco Electronics CorporationInventors: Keith McQuilkin Murr, Michael Eugene Shirk
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Patent number: 7518233Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.Type: GrantFiled: June 9, 2000Date of Patent: April 14, 2009Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.Inventors: Kouichi Takahashi, Kenichi Kasai, Takahiro Daikoku, Takayuki Uda, Toshitada Netsu, Takeshi Yamaguchi, Takahiko Matsushita, Osamu Maruyama
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Patent number: 7511968Abstract: Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.Type: GrantFiled: December 8, 2004Date of Patent: March 31, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Patent number: 7508063Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.Type: GrantFiled: April 5, 2005Date of Patent: March 24, 2009Assignee: Texas Instruments IncorporatedInventors: Robert M. Duboc, Terry Tarn
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Patent number: 7504670Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.Type: GrantFiled: June 7, 2006Date of Patent: March 17, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Satoshi Shiraishi, Yoichi Kazama
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Patent number: 7498673Abstract: An apparatus for heatsink attachment. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.Type: GrantFiled: November 21, 2006Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Elie Awad, John Jay Maloney
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Patent number: 7480152Abstract: A flexible circuit is populated with integrated circuits. Integrated circuits populated on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. In a preferred embodiment, the overall module profile does not, consequently, include the thickness of the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flex circuit may be aligned using tooling holes in the flex circuit and substrate. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs.Type: GrantFiled: December 7, 2004Date of Patent: January 20, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Patent number: 7470980Abstract: An apparatus and method for manufacturing a display device substrate are provided. In one embodiment, the apparatus comprises a clamp for clamping an edge of a plastic substrate, and a tension member applying tension along a surface of the plastic substrate by interacting with the clamp to strain the plastic substrate. Advantageously, the flexible plastic substrate is substantially prevented from deflecting in a manufacturing process thereby reducing defects in the display device substrate.Type: GrantFiled: July 25, 2006Date of Patent: December 30, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Woo-jae Lee
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Patent number: 7457491Abstract: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112) of the electrical-to-optical transmitter (100). A portion of the thermal conductive material extends approximately to an outer surface (120, 122 or 124) of a layer (114, 116 or 118) of the printed circuit board (104). The printed circuit board may comprise a planarized signal communications system or an optoelectronic signal communications system. In addition, the present invention provides a method for fabricating the heat sink wherein the electrical-to-optical transmitter disposed within a cavity of the printed circuit board is fabricated. New methods for flexible waveguides and micro-mirror couplers are also provided.Type: GrantFiled: September 21, 2006Date of Patent: November 25, 2008Assignee: Board of Regents, The University of Texas SystemInventors: Ray T. Chen, Chulchae Chol
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Patent number: 7444041Abstract: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112) of the electrical-to-optical transmitter (100). A portion of the thermal conductive material extends approximately to an outer surface (120, 122 or 124) of a layer (114, 116 or 118) of the printed circuit board (104). The printed circuit board may comprise a planarized signal communications system or an optoelectronic signal communications system. In addition, the present invention provides a method for fabricating the heat sink wherein the electrical-to-optical transmitter disposed within a cavity of the printed circuit board is fabricated. New methods for flexible waveguides and micro-mirror couplers are also provided.Type: GrantFiled: September 21, 2006Date of Patent: October 28, 2008Assignee: Board of Regents, The University of Texas SystemInventors: Ray T. Chen, Chulchae Choi
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Patent number: 7429760Abstract: Disclosed are a variable mask device for crystallizing a silicon layer capable of controlling a width and a length of an opening, and a method for crystallizing a silicon using the variable mask device. The variable mask device has a frame with an opening whose width is controlled by an X direction actuator and whose length is controlled by a Y direction actuator. A substrate on which a plurality of unit liquid crystal display panels are formed is provided. A laser beam is aligned through the opening and the silicon layer formed on the substrate is irradiated with the laser beam, thereby crystallizing the silicon layer. The substrate is moved in an X direction by scanning distance and the silicon layer is irradiated until the silicon layer is entirely crystallized.Type: GrantFiled: June 30, 2005Date of Patent: September 30, 2008Assignee: LG Display Co., Ltd.Inventor: JaeSung You
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Patent number: 7400038Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.Type: GrantFiled: August 12, 2005Date of Patent: July 15, 2008Assignee: Sony CorporationInventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
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Publication number: 20080164606Abstract: A deformable spacer for wafer bonding applications is disclosed. The spacer may be used to keep wafers separated until desired conditions are achieved.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Christoffer Graae Greisen, Lior Shiv, Paul N. Egginton
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Patent number: 7394658Abstract: A heat sink with a twist lock mounting mechanism. An electronic device may be mounted to the heat sink without the use of external fasteners, such as screws or rivets. Instead of using external fasteners, the heat sink includes resilient mounting flanges for securing an electronic device. Rotating an electronic device on the heat sink secures the electronic device in a friction fit with the resilient mounting flanges. Multiple electronic devices may be mounted to the heat sink, either manually or through an automated process.Type: GrantFiled: September 1, 2005Date of Patent: July 1, 2008Assignee: Harman International Industries, IncorporatedInventor: Philip S. McPhee
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Patent number: 7385296Abstract: A sensor includes: a first chip; a second chip disposed on the first chip through an adhesive member; and a stopper. The second chip is connected to the first chip through a bonding wire. The stopper limits a displacement of the second chip when the adhesive member is deformed. The stopper is disposed around the second chip. Since the displacement of the second chip is restricted, deformation of the bonding wire between the first and the second chips is also restricted.Type: GrantFiled: September 13, 2005Date of Patent: June 10, 2008Assignee: Denso CorporationInventor: Tameharu Ohta
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Patent number: 7360586Abstract: A mounting plate that is secured between a substrate and a component is used to mount a heat sink. The plate includes holes to accommodate the leads of the component and mounting flanges that partially surround the component and are used to mount the heat sink. In the mounted position, the heat sink is held in thermal communication with the component directly or through a thermally conductive material.Type: GrantFiled: July 31, 2003Date of Patent: April 22, 2008Assignee: Fujitsu LimitedInventors: Michael John Mania, Brian Patrick O'Donnell, Laurence Fox, Albert Pedoeem
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Patent number: 7349210Abstract: A grease cover (50) for protecting grease spread on a bottom surface of a heat sink (20) includes a base wall (51), a plurality of sidewalls (52a, 52b, 52c, 52d), a protecting space (53) between the base wall and the sidewalls, a holding space in an upper portion of the protecting space, and two projections (54). The protecting space is for accommodating the grease. The holding space is for receiving the heat sink therein. The projections extend from two opposite sidewalls of the grease cover. A top surface of each of the projections spaces a distance from the base wall, for supporting the bottom surface of the heat sink to enable the grease away from the base wall, when the heat sink is received in the holding space.Type: GrantFiled: November 18, 2005Date of Patent: March 25, 2008Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Jian-Qing Sheng, Chin-Lung Chen
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Patent number: 7323363Abstract: A integrated circuit housing includes a first clamping hardware, a second clamping hardware operatively connected to the first clamping hardware, and an integrated circuit stack comprising a top portion and a bottom portion, wherein the first clamping hardware contacts the top portion and the second clamping hardware contacts the bottom portion, and wherein a first shim is interposed between the bottom portion and the second clamping hardware.Type: GrantFiled: February 2, 2004Date of Patent: January 29, 2008Assignee: Sun Microsystems, Inc.Inventors: Donald A. Kearns, George C. Zacharisen, David K. McElfresh
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Patent number: 7324352Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.Type: GrantFiled: March 1, 2005Date of Patent: January 29, 2008Assignee: Staktek Group L.P.Inventor: Paul Goodwin
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Patent number: 7288842Abstract: Introduced is a power semiconductor module preferably a disk cell with a power semiconductor element arranged in the interior of the housing. In a preferred embodiment, the disk cell has two load and at least one auxiliary connection and the auxiliary connection extends from the power semiconductor element and ends at a corresponding exterior connection element. The exterior connection element of the auxiliary connection penetrates the housing and is a pen-type metal preform in the interior.Type: GrantFiled: December 8, 2005Date of Patent: October 30, 2007Assignee: Semikron Elektronik GmbH & Co KGInventor: Ludwig Hager
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Patent number: 7282789Abstract: A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the assembly. The semiconductor devices may include semiconductor dice, or they may be devices that have yet to be separated from other devices carried by the same substrates.Type: GrantFiled: September 1, 2004Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: RE41559Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.Type: GrantFiled: August 31, 2006Date of Patent: August 24, 2010Assignee: International Rectifier CorporationInventor: Charles S. Cardwell