Devices Held In Place By Clamping Patents (Class 257/726)
  • Patent number: 7277299
    Abstract: In a multi-device holding structure for integrally holding two heat generative elements which are transistors having through-holes so as to be mounted on a base plate, and a heat sensitive element which is a temperature fuse sandwiched between the heat sensitive elements and is mounted on the base plate, the heat generative elements and the heat sensitive element are covered with a metallic holding member provided with first flat spring segments for urging the heat generative elements on both ends as well as inserting segments extending upward and inserted into the through-holes, and second flat spring segments for supporting the sides of the heat sensitive element.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: October 2, 2007
    Assignee: Funai Electric Co., Ltd.
    Inventor: Katsuyuki Yoshida
  • Patent number: 7271473
    Abstract: A semiconductor power circuit in which multiple field effect transistor dies are solder connected between opposed contact surfaces of overlying flat conductors and are clamped by means of spring clips which are arranged in symmetrically opposed relationship. A circuit board also disposed between the clamped surfaces is protected from the clamping forces by means of a soft paper layer with holes registering with similar holes in the circuit board to permit solder pads to pass there through.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: September 18, 2007
    Assignee: Yazaki North America, Inc.
    Inventors: Sam Yonghong Guo, Myron Udell Trenne
  • Publication number: 20070194444
    Abstract: A protecting apparatus is provided for protecting a chip that is mounted on a subminiature circuit board. The protecting apparatus includes a supporting seat for mounting the subminiature circuit board thereon, and a protective cover for receiving the subminiature circuit board and the supporting seat therein. The supporting seat includes a locking element. The protective cover includes a connecting element corresponding to the locking element. The supporting seat is fixed in the protective cover via the locking element engaging with the connecting element.
    Type: Application
    Filed: July 14, 2006
    Publication date: August 23, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Tang Peng, Hung-Yi Wu, Guang-Yi Zhang, Jiang-Ping Zhu, Ming-Ke Chen
  • Patent number: 7244967
    Abstract: A method of fabricating an integrated circuit sensor package. The method comprises the steps of: 1) mounting a substrate on a first mold block, the substrate comprising a substantially planar material having a first substrate surface and a second substrate surface that contacts a mounting surface of the first mold block; 2) placing an adhesive on the first substrate surface; 3) placing an integrated circuit sensor on the adhesive; and 4) pressing a second mold block against the first substrate surface. The second mold block comprising a cavity portion for receiving the integrated circuit sensor, a contact surface surrounding the cavity portion, and a compliant layer mounted with the cavity portion. Pressing the second mold block against the first substrate surface causes the contact surface to form with the first substrate surface a seal surrounding the integrated circuit sensor.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: July 17, 2007
    Assignee: STMicroelectronics, Inc.
    Inventors: Michael J. Hundt, Tiao Zhou
  • Patent number: 7227261
    Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden, Terry R. Lee
  • Patent number: 7193852
    Abstract: The present invention relates to a control unit (1), for automotive applications in particular, with: a frame (8) that includes a recess (9) across which electrical conductive tracks (10) extend to supply electrical power; a base plate (11) that is inserted in the frame (8); a circuit carrier (12) on which electronic components are mounted and which is installed on the base plate (11); an electrical connection (14) for connecting the circuit carrier (12) with the conductive tracks (10); and a cover (4) for hermetically sealing the control unit (1), the cover including a shaped section that is insertable in the associated recess (9) in the frame (8); whereby a sealing gel (16) is provided in recess (9) with a viscosity such that the sealing gel (16) can flow around the electrical conductive tracks (10) that extend across the recess (9). The present invention further relates to a manufacturing method for manufacturing a control unit (1) of this type.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: March 20, 2007
    Assignee: Robert Bosch GmbH
    Inventor: Gerhard Wetzel
  • Patent number: 7185423
    Abstract: A method of improving shock and vibration isolation of a CGA integrated package which utilizes solder column grid arrays and that includes a substrate and a package lid, includes providing a support frame attached at an attachment point to the substrate or the package lid and at a second attachment point to the circuit board. Isolation material is provided at the attachment point of the support frame to the substrate or package lid, or at the second attachment point of the support frame to the circuit board.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas J. Augustin, Christopher G. Malone
  • Patent number: 7173340
    Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: February 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Binling Zhou, James L. Todsen, Brian D. Johnson
  • Patent number: 7170169
    Abstract: A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies include stamped and formed contacts having an insulative plastic molded over a central section of the contact. A grounding clip surrounds the housing and is conductively connected to the substrate, and has spring arms which are connectable to heat sink hardware on one side thereof and to a printed circuit board on the other side.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: January 30, 2007
    Assignee: Tyco Electronics Corporation
    Inventors: David A Trout, Richard N Whyne
  • Patent number: 7170165
    Abstract: An assembly includes a circuit board with a ball grid array device attached to a first side of the circuit board. A brace surrounding the ball grid array device has a series of mounting holes and a series of members extending between the mounting holes. The brace is removably secured to the first side of the circuit board at the mounting holes.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 30, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Thomas E. Berto, Anirudh N. Vaze
  • Patent number: 7166915
    Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree, James M. Wark
  • Patent number: 7138708
    Abstract: An electronic system having a sandwich design and including two carriers, each carrier having a printed circuit layer, the upper printed circuit layer being positioned on different planes.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: November 21, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Rainer Topp, Dirk Balszunat, Christoph Ruf, Andreas Fischer
  • Patent number: 7105858
    Abstract: An LED display assembly, comprising a grid of electrical conductors; light emitting diodes in association with the grid and in electrical communication with the conductors that provide power for LED operation, the grid operable to receive heat from the diodes during diode operation, and the array configured for passing coolant fluid for transfer of heat to the fluid. LED packages adjustable relative to a mounting grid, are also provided.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: September 12, 2006
    Assignee: OnScreen Technologies
    Inventor: John M. Popovich
  • Patent number: 7095113
    Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 22, 2006
    Assignee: Diodes Incorporated
    Inventors: Tan Xiaochun, Shi Jingping
  • Patent number: 7045884
    Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: May 16, 2006
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 7045891
    Abstract: A through socket includes a socket body, which can load the plurality of memory modules, and a plurality of internally connected socket conductors arranged to electrically connect the memory modules when loaded. A turn around socket includes a socket body for loading at least one memory module and connecting a contact of one surface of a loaded memory module to a contact of the other surface. Using at least one through socket and at least one turn around socket, the memory system can extend a plurality of memory modules on a printed circuit board (PCB). A memory module adapted for use in the memory system has four contacts arranged at both ends and on both surfaces.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: May 16, 2006
    Assignee: Samsung Electronic Co., Ltd.
    Inventor: Jung-Hwan Choi
  • Patent number: 7042086
    Abstract: A stacked semiconductor module encompasses (a) a upper switching element having a first semiconductor chip, a first top electrode disposed at a top surface of the first semiconductor chip, a first bottom electrode disposed at a bottom surface of the first semiconductor chip, and a first control electrode configured to control conduction between the first top and first bottom electrodes; (b) a first wiring plate disposed beneath the upper switching element, electrically connected to the first bottom electrode; and (c) a lower switching element disposed beneath the wiring plate, having a second semiconductor chip, a second top electrode disposed at a top surface of the second semiconductor chip, electrically connected to the first wiring plate, a second bottom electrode disposed at a bottom surface of the second semiconductor chip, and a second control electrode configured to control conduction between the second top and second bottom electrodes.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: May 9, 2006
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshio Shimoida, Toshiro Shinohara, Tetsuya Hayashi, Masanori Yamagiwa
  • Patent number: 7012331
    Abstract: A semiconductor package is mounted to a support plate through a base. The base is inserted between a rear face of the semiconductor package and a front face of the support plate. An electrical connection mechanism is provided to connect the semiconductor package to the support plate pass. This mechanism passes through the base. The mounting of the semiconductor package is accomplished by a variety of structures to fasten the package onto the said support plate. These structures cooperate with and are placed below the rear face of the semiconductor package.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: March 14, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Rémi Brechignac, Kevin Channon, Juan Exposito
  • Patent number: 7005739
    Abstract: The stackable power semiconductor module comprises electrically conductive base plates, an electrically conductive cover plate and a plurality of semiconductor chips. The semiconductor chips are arranged in groups of several on separate base plates in preassembled submodules. The base plates are moveable towards the cover plate. The submodules are paralleled inside the module housing. The submodules are fully testable according to their current ratings. Altering the number of submodules paralleled inside the housing can vary the overall current rating of a module.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: February 28, 2006
    Assignee: ABB Schweiz AG
    Inventors: Stefan Kaufmann, Thomas Lang, Egon Herr, Mauro Nicola, Soto Gekenidis
  • Patent number: 6969903
    Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor.
    Type: Grant
    Filed: January 19, 2004
    Date of Patent: November 29, 2005
    Assignee: International Business Machines Corporation
    Inventors: Ebenezer E. Eshun, Steven H. Voldman
  • Patent number: 6919632
    Abstract: A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: July 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Sei
  • Patent number: 6914280
    Abstract: Since a 5 GHz-band broadband has a frequency twice that of 2.4 GHz, the parasitic capacitance greatly influences deterioration in isolation of a switching device used in this frequency region. Therefore, to improve isolation, a shunt FET is added to the device. The switching device also includes a protecting element that has a first n+-type region, an insulating region and a second n+-type region. This protecting element is connected in parallel between two electrodes of the shunt FET. Since electrostatic charges are discharged between the first and second n+-type regions, the electrostatic energy reaching an operation region of the shunt FET can be reduced without an increase in parasitic capacitance.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 5, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Yoshibumi Nakajima, Hidetoshi Ishihara
  • Patent number: 6894396
    Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
  • Patent number: 6891730
    Abstract: Miniaturized circuit housing to encapsulate and provide external contacts for at least one integrated circuit, in particular of the flip-chip or wafer-level-package type, with a housing floor, the lower surface of which bears housing contact elements for making external contact and the upper surface of which is electrically connected to circuit contact elements on the lower surface of the circuit, wherein a housing lid is provided, in particular opposite the housing floor, which presses the circuit with the circuit contact element resiliently against the upper surface of the housing floor, and between the circuit contact elements and the housing floor there is no connection that fixes their materials permanently together.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: May 10, 2005
    Assignee: F & K Delvotec Bondtechnik GmbH
    Inventor: Farhad Farassat
  • Patent number: 6873037
    Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 29, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 6870258
    Abstract: A fixture suitable for coupling a lid to a substrate having a semiconductor chip coupled thereto and a method for coupling the lid to the substrate. A support structure has a cavity having a floor and a pedestal protruding from the floor. A guide extends from the support structure. A compression mechanism is coupled to the guide wherein the compression mechanism includes an actuator plate coupled to a compression plate by a compressible means. An actuator is coupled to the compression mechanism. A packaging substrate having a semiconductor chip is mounted to the packaging substrate and a lid is mounted over the semiconductor chip to form a semiconductor component. The semiconductor component is placed on a support structure and the actuator is activated to urge the compression plate to apply a uniform force against the lid.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: March 22, 2005
    Assignee: Advanced Micro Devices
    Inventor: Seah Sun Too
  • Patent number: 6864573
    Abstract: A two piece electronic component heat sink and device package comprising a first piece configured to retain electronic components, and a second piece having a hinge region configured to moveably connect the second piece to the first piece, and a snap lock region opposite the hinge region, the snap lock region configured to secure the second piece to the first piece. A two piece electronic component heat sink and device package for a circuit board comprising: a first piece having an index slot for retaining said circuit board, and a second piece having a hinge region configured to pivotably connect the second piece and the first piece, and a snap lock region configured to secure the second piece to the first piece.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: March 8, 2005
    Assignee: DaimlerChrysler Corporation
    Inventors: Michael F Robertson, Gary L Brown
  • Patent number: 6861747
    Abstract: (1) A thermal enhanced type of BGA package, in which a metal heat sink is joined to one side of a plastic circuit board which has a cutout space in the central portion, comprised of a clamping member joining the plastic circuit board and the heat sink. A caulking member, a rivet, a screw, an eyelet, or a tubular rivet could be used as the clamping member. It is preferable that a dam member is definitely attached by the clamping member. (2) Another thermal enhanced type of BGA package, in which a circuit pattern is provided in the plastic circuit board and the heat sink and/or the dam member are electrically connected to a part of the circuit pattern through the clamping member. It is preferable to use the clamping member coated by solder.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: March 1, 2005
    Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.
    Inventors: Takeshi Miyazaki, Akihiro Hamano, Shigehisa Tomabechi
  • Patent number: 6859367
    Abstract: Heat sink attachment components are provided comprising retention bolts with a coil spring captured between the head of the retention bolt and a retention lock flange of a retention lock. A portion of each retention bolt shaft is retained and in frictional engagement with socket bores of a mounting socket. A moderate interference fit between the retention lock and the retention bolt prevents unintended decoupling. While engaged, the compressed coil spring urges against the retention lock flange, with the retention lock flange in urging engagement with the heat dissipation side of a heat sink base, with the heat sink base in urging engagement with thermal interface material on the top of the microelectronic package. The urging engagement of the coil springs provide a constant bias for urging engagement between the components.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventor: Peter A. Davison
  • Patent number: 6856503
    Abstract: A control device is for a commercially available switchgear and an electronic power module. Compactness of the device is improved so that it can be used in a switchgear cabinet. To this end, the power module is placed onto the switchgear on the side facing away from its bottom wall and the dimensions of the power module are adapted to the base contour of the switchgear so that the peripheral contour of the power module extends beyond the base contour only slightly, if at all, wherein at least the width of the contactor does not extend beyond it.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: February 15, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Walter Apfelbacher, Norbert Reichenbach
  • Patent number: 6836016
    Abstract: An apparatus comprises a first device comprising a carrier having one or more conductive areas to form a portion of an electromagnetic coupler and a socket to mount the first device relative to a second device having one or more conductive areas to form the electromagnetic coupler. The socket defines a coupler region in which the carrier is inserted to align the carrier relative to the second device.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: December 28, 2004
    Assignee: Intel Corporation
    Inventors: Nandu J. Marketkar, Thomas F. Knight, Jr.
  • Patent number: 6836005
    Abstract: A semiconductor device includes a semiconductor package, a substrate provided under the semiconductor package, a metal substrate provided on the semiconductor package, and a fixing member positioning the semiconductor package and the metal substrate on the substrate. The substrate is provided with a hole passing though the substrate. A portion of the fixing member is inserted into the hole and a tip of the fixing member contacts a fourth terminal. Semiconductor package has a first main surface, a second main surface provided opposite to the first main surface, and a first terminal provided at the first main surface.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: December 28, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shohei Moriwaki
  • Patent number: 6833618
    Abstract: The invention provides a memory system that allows connection of a memory controller to each of plural memory modules in an equal distance. The memory system includes a memory controller, three memory modules, a single socket which the three memory modules can be inserted into and pulled out from, and a mother board on which the memory controller and the socket are mounted, etc. And, the memory controller and each of the memory modules are connected in an equal distance through the socket pins of the socket that are branched from bus wirings on the mother board. The socket is furnished with three sets of the plural socket pins in a radial form, in correspondence with each of the memory modules. The socket has two types of structures: one has three module-board contacts for one board-bus connection, and the other has one module-board contact for one board-bus connection.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takao Ono, Hironori Iwasaki, Mitsuya Tanaka
  • Patent number: 6825558
    Abstract: The present invention relates to a carrier module for micro-BGA (&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 30, 2004
    Assignee: Mirae Corporation
    Inventor: Sang Jae Yun
  • Patent number: 6812565
    Abstract: There is provided a multi-chip module which can vary functions of a memory chip at the time of loading or after loading, to the wiring board, the memory chip having formed an external connecting terminal with the wafer process. Two kinds of multi-chip modules having different functions such as word configuration and operation mode is realized using the identical memory chips by preparing for two kinds of module substrate of different patterns of wiring including the power supply voltage wiring and the ground potential wiring and then loading a memory chip and a control chip to these two kinds of module substrate.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: November 2, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Nishimoto, Mitsuaki Katagiri
  • Patent number: 6791184
    Abstract: A support assembly for supporting an integrated circuit package with an array of solder columns extending from a bottom surface of the integrated circuit package to a circuit board preferably includes: a pair of shims for supporting the integrated circuit package, the shims being positioned along opposite edges of the integrated circuit package and placed between and abutting the integrated circuit package and the circuit board; and a retention clip for aligning and securing in place the pair of shims.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey L Deeney, Laszlo Nobi, Joseph D. Dutson
  • Patent number: 6788540
    Abstract: The present invention relates to a cage for holding an optical transceiver module in electrical contact with a host circuit board. The cage includes front, middle and rear sections, and facilitates the insertion of the optical transceiver into the cage, as well as providing electromagnetic shielding and facilitating thermal dissipation. Typically, the cage is for use with an optical transceiver module including an integral heat sink cover or with an optical transceiver module including an external heat sink mounted over top of the cage. Various embodiments illustrate different schemes for maximizing heat dissipation by providing large openings in the middle section of the cage, as well as mounting surfaces on the front and rear sections for mounting external heat sinks. One or more crossbars are provided for guiding the transceiver module during insertion.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: September 7, 2004
    Assignee: JDS Uniphase Corporation
    Inventors: Bruce P. Kruger, Gary Heitkamp, Scott Michael Branch
  • Patent number: 6781840
    Abstract: Fastening members such as tapping screws and rivers having a shaft are used to fasten objects such as circuit elements, a circuit board and a casing to a target object such as a heat sink of a circuit unit. The target object has a uniform cross-sectional shape along a specified direction, having grooves formed over the entire length along this direction. The fastening members are passed through the objects to be fastened and inserted into these grooves perpendicularly to be affixed to the target object so as to fasten the objects to be fastened onto the target object.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: August 24, 2004
    Assignee: Omron Corporation
    Inventors: Yoshihiro Ikushima, Yutaka Ohkubo, Hidetoshi Yoshikawa
  • Patent number: 6780767
    Abstract: Semiconductor components in a wafer assembly, in which the components are connected to a frame by means of in each case one holder and are formed from the same silicon wafer. The holder connects the respective component to the frame on one side and has a desired breaking point. The desired breaking point is designed as a V-shaped groove, the surfaces of which form crystal planes. According to the method, the patterning for production of the holder takes place on the wafer back surface, with subsequent wet chemical anisotropic etching of the V-groove. In this way, the holder is produced independently of the processing of the wafer front surface, and when the semiconductor component is removed a defined broken edge is formed without there being any risk of the semiconductor component being damaged.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Nanoworld AG
    Inventor: Stefan Lutter
  • Patent number: 6738258
    Abstract: The power semiconductor module (1) comprises a housing (5), a covering panel (11) and at least two submodules (21, 22). The submodules (21, 22) each comprise at least one semiconductor chip, which has two main electrodes which are electrically conductively connected to main connections (3, 4) of the submodules. The submodules (21, 22) are arranged alongside one another, and one of their two main surfaces is pressed against the covering panel (11) of the module. The submodules are electrically connected in series. The maximun blocking voltage of the module is doubled by connecting the submodules, which are arranged alongside one another, in series. This reduces the length and the costs of the stack for hihg-voltage switch since fewer components are required for the same blocking voltages, in particular fewer modules and cooling elements.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: May 18, 2004
    Assignee: ABB Research LTD
    Inventors: Bo Bijlenga, Fabian Zwick, Stefan Linder, Patrick Erne
  • Patent number: 6730999
    Abstract: A chip carrier for temporarily connecting a semiconductor chip to a testing device. The chip carrier includes a substrate having a first set of contact points for electrically engaging the testing device and a second set of contact points to be connected with the contact elements of the semiconductor chip. The semiconductor chip is disposed on the substrate and is substantially covered by a cover member. One or more clips are in contact with the cover member and are used to secure the semiconductor chip in position. The clips have a first member removably attached to the substrate and a second member separated from the first member and in contact with the cover member. As the second member is displaced from an unstressed position, a force is generated by the clip and transferred to the cover member and the semiconductor chip. The chip carrier reliably secures the semiconductor chip while occupying a relatively small space over the semiconductor chip.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek Gochnour, Alan Wood
  • Patent number: 6724081
    Abstract: A replaceable integrated circuit device which replaces the connecting socket, the interposer and the pins in prior art with plural solder balls on the bottom of the integrated circuit package contacting and connecting the corresponding contact pad on the circuit board for electrical conduction. The contacting surface of the solder balls and the corresponding contact pad can be made as plane or as curve as possible to increase the contacting area. More over, there are many buckling apparatus placed on the circuit board to buckle the integrated circuit package and the circuit board firmly and to provide the extra downward force to make the solder balls and the corresponding contact pad contact and connect each other tightly. In the present invention, for the solder balls contacting the contact pads of the circuit board directly, which reduce the space that a connecting socket used in prior art and improve the usage ratio of the layout on a circuit board.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: April 20, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Kwun-Yao Ho, Kung Moriss, Lin-Chou Tung
  • Patent number: 6710436
    Abstract: One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 23, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: David L. Harris, Robert J. Drost, Ivan E. Sutherland
  • Patent number: 6683378
    Abstract: A method for singulating a substrate containing semiconductor components is performed using a nest for holding the substrate, a prestage alignment base for aligning the substrate during a prestage alignment step, and a vacuum cutting base for holding the nest and the substrate during a cutting step. The prestage alignment base includes locator pins configured to engage locator openings on the substrate to align the substrate on the nest. As the cutting base does not include the locator pins, the cutting step can be performed without saw scrap collecting on the locator pins. A system for performing the method includes the nest and the prestage alignment base having the locator pins configured to engage the locator openings on the substrate. The system also includes the sawing base which includes pedestals with vacuum conduits for holding the substrate stationary on the nest for sawing.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jason C. Wing, Gregory M. Chapman
  • Publication number: 20040012085
    Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 22, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
  • Patent number: 6677669
    Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 13, 2004
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 6678163
    Abstract: A housing arrangement for a plurality of semiconductor chips (1) is disclosed, in which each of the chips is received in a respective frame or cassette (4), there being a first electrically conductive member (5), having portions (6) which are in electrical connection with one face of each of the chips and a second electrically conductive member (7), having portions (8) which are in electrical connection with an opposite face of each of the chips.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: January 13, 2004
    Assignee: Westcode Semiconductors Limited
    Inventors: Howard Donald Neal, Robert Charles Irons
  • Patent number: 6639800
    Abstract: A heat sink subassembly may include a retainer comprising several attachment points, a heat sink coupled to the retainer, and a force-generating device. The heat sink includes several fins, one of which is shorter than the other fins. The force-generating device is coupled to at least one of the attachment points and to the first fin. The force-generating device is configured to exert a force that keeps the heat sink securely coupled to the retainer when the force-generating device is coupled to the attachment points.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: October 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lewis Michael Eyman, Roger Q. Paulsel, Stanley O. Sharp, James W. Delso
  • Patent number: 6634095
    Abstract: An installation apparatus of installing a land grid array (LGA) multi-chip module assembly to a printed wiring board is provided. A module holding member is attached to the printed wiring board. The module assembly is inserted into the module holding member. The module assembly is retained to the module holding member, which facilitates mechanical actuation of the LGA compression hardware. The module assembly is electrically grounded to the printed wiring board while the module assembly is retained to the module holding member.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: October 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: John L. Colbert, John S. Corbin, Jr., Roger D. Hamilton, Danny E. Massey, Arvind K. Sinha, Charles C. Stratton
  • Patent number: 6600661
    Abstract: A support assembly useful for supporting an integrated circuit package having an array of solder columns extending to a circuit board when the integrated circuit package is mounted on the circuit board. The support assembly includes a support member for supporting the integrated circuit package and having a ramped surface. A biasing member associated with the support member couples the ramped surface to the integrated circuit package such that the support member resists downward movement of the integrated circuit package. The support member may include a plurality of support members with ramped surfaces which cooperate to raise a combined height of the support members. A related method of supporting an integrated circuit package is also provided.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: July 29, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jeffrey L. Deeney