Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.

Abstract: The present invention relates to a gallium nitride-based compound semiconductor device and a method of manufacturing the same. According to the present invention, there is provided a gallium nitride-based III-V group compound semiconductor device comprising a gallium nitride-based semiconductor layer and an ohmic electrode layer formed on the gallium nitride-based semiconductor layer. The ohmic electrode layer comprises a contact metal layer, a reflective metal layer, and a diffusion barrier layer.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.

Abstract: A first semiconductor chip and a second semiconductor chip which form a stack are mounted on a module substrate by deflecting a center position of the semiconductor chips from the module substrate. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are directly connected with a wire. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is longer, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are combined with the corresponding bonding lead on the module substrate with a wire.

Abstract: A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.

Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: A composite conductive film formed of a polymer-matrix and a plurality of conductive lines less than micro-sized and its fabricating method are provided. The conductive lines are arranged parallel and spaced apart from each other so as to provide anisotropic conductivity. The present conductive film can serve as an electrical connection between a fine-pitch chip and a substrate. Additionally, an adhesive layer is formed on two opposite sides of the conductive film along its conductive direction to increase adhesive areas. The strength and reliability of the package using the conductive film are thus enhanced.

Abstract: A wiring structure of a semiconductor device may have an insulation layer, a spacer and a plug. The insulation layer may be provided on a substrate and may have an opening through which a contact region of the substrate is exposed. The spacer may be provided on a sidewall of the opening. The plug may fill the opening and may include a polysilicon pattern doped with impurities, a metal silicide pattern, and a metal pattern sequentially provided on the substrate.

Abstract: A multilayer substrate, comprising a first substrate, a connector and a second substrate, is disclosed. The first substrate has a circuit pattern. The connector, coupling onto the first substrate, has a ring structure, in which a plurality of holes are separated a predetermined distance from one another. The second substrate, coupling onto the second substrate by inserting the connector, has a circuit pattern, which is electrically connected to a circuit pattern formed on the first substrate using the plurality of holes formed on the connector. A multilayer substrate and a method for producing it in accordance with the present invention can shield the EMI generated by a high-speed switching element.

Abstract: A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: A semiconductor device comprises a semiconductor integrated circuit, an external connection terminal connecting the semiconductor integrated circuit to an external device, and a plurality of tin or tin-alloy plating layers formed on the external connection terminal as multiple unleaded metal plating layers. The multiple unleaded metal plating layers comprise a first layer made of a tin alloy and provided as an inner layer of the multiple unleaded metal plating layers, the tin alloy of the first layer containing as a second element one of bismuth, silver, copper, indium, and zinc, and a second layer made of either 100% tin or a tin alloy and provided as an outer surface layer of the multiple unleaded metal plating layers, the 100% tin or the tin alloy of the second layer having a percentage of tin content greater than that of the first layer.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.

Abstract: A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment, the substrate is adapted to curl to the same degree as the die to form a uniform gap between the substrate and die across the boundary there between. In another embodiment, solder used to bond the die and substrate is applied such that the volume deposited varies based on the expected gap between the die and substrate when heated to the melting temperature of the solder.

Abstract: A vertical laminated electrical switch circuit includes a first, second, and third ceramic substrate positioned in juxtaposed relationship relative to each other. The circuit also includes a first and second electrical device electrically coupled to each other. The first electrical device is coupled to the first and second substrates and positioned there between. The second electrical device is coupled to the second and third ceramic substrates and positioned there between. In some embodiments, multiple electrical devices may be coupled to a single substrate.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a substrate coupled to a first material and a second material. The first and second materials may comprise adjacent metals, and may have different coefficients of thermal expansion sufficient to reduce the amount of substrate warp that can occur due to heating and cooling.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.

Abstract: A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.

Abstract: A coated electrically conductive substrate has particular utility where there are multiple closely spaced leads and tin whiskers constitute a potential short circuit. This electrically conductive substrate has a plurality of leads separated by a distance capable of bridging by a tin whisker, a silver or silver-base alloy layer coating at least one surface of at least one of the plurality of leads, and a fine grain tin or tin-base alloy layer directly coating said silver layer. An alternative coated electrically conductive substrate has utility where debris from fretting wear may increase electrical resistivity. This electrically conductive substrate has a barrier layer deposited on the substrate that is effective to inhibit diffusion of the substrate into a subsequently deposited layers, which include a sacrificial layer deposited on the barrier layer that is effective to form intermetallic compounds with tin, and a low resistivity oxide metal layer deposited on the sacrificial layer.

Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.

Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.

Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.

Abstract: On a piezoelectric substrate 23, there are provided surface acoustic wave devices F1 and F2 in which predetermined circuit patterns are formed, and a package substrate 11 comprising side vias 16 formed in a caved manner in the thickness direction on side surfaces on which the surface acoustic wave devices are mounted. When the side vias 16 are each assumed to have the opening width ? and the maximum depth D, a size satisfying ?/2<D is assumed. Thereby, it is possible to prevent protrusion of a soldering fillet applied on the side via.

Abstract: An integrated circuit according to the present invention includes first, second and third plane-like metal layers. A first transistor has a first control terminal and first and second terminals. The second terminal communicates with the first plane-like metal layer. The first terminal communicates with the second plane-like metal layer. A second transistor has a second control terminal and third and fourth terminals. The third terminal communicates with the first plane-like metal layer. The fourth terminal communicates with the third plane-like metal layer. A fourth plane-like metal layer includes first, second and third contact portions that are electrically isolated from each other and that are connected to the second plane-like metal layer, the first plane-like metal layer and the third plane-like metal layer, respectively.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: An interconnection substrate includes: an interconnection layer region where at least a first conductor layer and a second conductor layer are vertically stacked in that order on a substrate, with the first conductor layer and second conductor layer containing conductive particles and a binder, wherein the first conductor layer and second conductor layer stacked in the interconnection layer region have conductive particles different in average particle size from each other. As a result, only an intended region can have low resistance.

Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.

Abstract: A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

Abstract: Disclosed is a method of forming a self-aligned contact structure using a sacrificial mask layer. The method includes forming a plurality of parallel interconnection patterns on a semiconductor substrate. Each of the interconnection patterns has an interconnection and a mask pattern, which are sequentially stacked. Interlayer insulating layer patterns are formed to fill gap regions between the interconnection patterns. The mask patterns are partially etched to form recessed mask patterns that define grooves between the interlayer insulating layer patterns. Then, sacrificial mask patterns filling the grooves are formed. A predetermined region of the interlayer insulating layer patterns is etched using the sacrificial mask patterns as etching masks to form a self-aligned contact hole that exposes a predetermined region of the semiconductor substrate. A spacer is formed of a sidewall of the self-aligned contact hole, and a plug surrounded by the spacer is formed in the self-aligned contact hole.

Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.

Abstract: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The lower layer of the bilayer structure is at the level of the wiring layer and the upper layer of the bilayer structure extends above the level of the wiring layer. The bilayer wiring structure is formed by depositing the upper and lower electrically conductive layers separated by a protective electrically conductive layer over the substrate, etching the upper electrically conductive layer and a portion of the protective electrically conductive layer, and thereafter separately etching the lower electrically conductive layer to form the wiring layer over the substrate. The method also includes connecting a wirebond to the upper layer of the bilayer structure.

Abstract: A semiconductor device includes a base, a semiconductor element having a plurality of electrodes, a plurality of conductive lines connected to the electrodes of the semiconductor element, plating stubs attached to the conductive lines, and a plurality of wiring layers formed in a plurality of layers on the base. The plating stub attached to a first conductive line, and the plating stubs attached to one or a plurality of second conductive lines adjacent to the first conductive line, exist in different conductive wiring layers.

Abstract: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.

Abstract: The present invention is directed to a new bonding pad structure that includes a copper pad and a pad surface finish comprising multiple layers of solder. The multiple layers of solder include at least a layer of eutectic solder (or a layer of pure-Sn solder) covering the copper pad and a layer of high-Pb solder covering the layer of eutectic solder (or the layer of pure-Sn solder). Since the layer of high-Pb solder is significantly thicker than the eutectic solder layer (or the layer of pure-Sn solder), there is insufficient tin supply in the eutectic solder (or the layer of pure-Sn solder) for forming a thick Cu/Sn intermetallic layer on the copper pad. Instead, a thin Cu/Sn intermetallic layer is formed on the copper pad and there is less likelihood of forming a crack in the thin Cu/Sn intermetallic layer.

Abstract: A method for fabricating a flip-chip semiconductor device having plural conductive polymer bumps includes forming plural molds on a substrate using a photolithographic technique; filling the molds by applying and spinning a layer of conductive polymer material onto the substrate; polishing the conductive polymer material layer to remove excess conductive material from a surface of the substrate; and stripping the plural molds from the substrate to reveal the plural bumps. In various aspects of disclosure, either positive resist or negative resist may be used. The electrical contact resistance compares favorably with squeegee-based bumps; there is an improvement in the contact resistance of the bumps patterned using polishing techniques in comparison to that of squeegee-based conductive polymer bumps.

Abstract: The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, and methods for making the same, wherein the metallization structure includes a substrate with a substantially planar upper surface, a foundation metal layer disposed on a portion of the substrate upper surface, a primary conducting metal layer overlying the foundation metal layer, and a metal spacer on the sidewalls of the primary conducting metal layer and the foundation metal layer.

Abstract: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.

Abstract: A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the semiconductor substrate to the connection region. A contact plug is provided in the contact hole. A clearance formed in the contact plug is formed with a buried conductive film consisting of a material different from the contact plug. The buried conductive film has a continuous surface without forming a step with the surface of the contact plug.

Abstract: The invention provides a method for forming bond pad openings through a three-layer passivation structure, which protects the semiconductor device prior to bonding and packaging. Two passivation layers are formed over a semiconductor device with bond pads formed thereon. Openings are formed through the passivation layers to expose the bond pads. The openings are then filled with a photoresist material before depositing a polyimide layer over the passivation layers. Openings are formed in the polyimide layer so as to expose the filled openings. The photoresist material in the filled openings is subsequently removed to expose the bond pads.

Abstract: A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Abstract: A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.

Abstract: An improved method and solder composition for kinetically controlled part bonding. The method involves applying at least a first chemical element layer of an intermetallic compound to a first part and applying at least a second chemical element layer of the intermetallic compound to a second part. The first and second parts are placed together so that the chemical element layers contact each other. The parts are heated from a storage temperature to a bonding temperature which is slightly above a first melting temperature that melts the chemical element layer of one of the first and second parts into a liquid mixture. The composition of liquid mixture varies with time during heating due to the formation of the intermetallic compound therein by progressive incorporation of the other one of the first and second chemical element layers into the mixture.

Abstract: The present invention includes one wiring or a plurality of wirings and an MIM capacitor formed by capacity coupling of a lower electrode which is connected to an upper surface of the wiring(s) and an upper electrode. The lower electrode is comprised of a material preventive of diffusion of a material of the wiring(s), and it embraces the wiring(s).

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.