Abstract: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip 30 and a substrate, the semiconductor chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semiconductor chip 30 can be enhanced.

Abstract: The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.

Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.

Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.

Abstract: A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconductor substrate. An IP (Intellectual Property) region comprises a plurality of semiconductor devices formed on the semiconductor substrate and has a predetermined function. A first wiring layer is in the lower layer wiring region above the semiconductor substrate and a second wiring layer is above the IP region. A third wiring layer is in the upper wiring region of the gate array region. The third wiring layer is wider than the first and second wiring layers.

Abstract: A lead frame for a semiconductor package and a method for manufacturing the lead frame. In the manufacture of the lead frame, a protective layer is formed with nickel (Ni) or Ni alloy on a metal substrate, an intermediate layer is then formed with palladium (Pd) or Pd alloy on the protective layer. Then, Pd and gold (Au) are alternately plated on the surface of the intermediate layer to form an outermost layer including both Pd and Au particles thereon.

Abstract: A small semiconductor device close in size to a semiconductor chip which prevents warping of semiconductor chips or wafer and delamination of an interface from an interlayer insulating film, both caused by thermal stresses of a rewiring layer. The use of a Cu composite alloy containing 80 vol. % or less of Cu2O, which alloy has a smaller linear thermal expansion coefficient and a smaller elastic modulus than those of pure copper, as a main material of the rewiring layer can reduce the thermal stresses in the rewiring layer, realizing a semiconductor device in which warping of semiconductor chips or wafer and delamination of layers will not easily occur.

Abstract: A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in contact with the insulating layer in the dielectric organic layer, wherein the upper surface of the interconnection layer is formed higher than the upper surface of the dielectric organic layer, and a method of manufacture thereof.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A semiconductor chip is mounted in face-up disposition, with a contact-bearing front surface facing away from a substrate such as a circuit panel, and with a rear face facing toward the substrate. A backing element having terminals is disposed between the rear face of the chip and the substrate, and the terminals of the backing element are connected to contact pads on the substrate. The terminals of the backing element are movable with respect to the chip to compensate for differential thermal expansion of the chip and substrate.

Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).

Abstract: An electronic device includes a first conductive polymer layer sandwiched between a first external metal foil electrode and a first internal metal foil electrode, a second conductive polymer layer sandwiched between a second internal metal foil electrode and a second external metal foil electrode, a layer of fiber-reinforced epoxy resin bonding the first and second internal electrodes together, a first terminal providing electrical contact between the first internal electrode and the second external electrode, and a second terminal providing electrical contact between the second internal electrode and the first external electrode. In a preferred embodiment, the polymer layers exhibit PTC behavior, and the terminals are formed by a solder layer applied over a plated layer of conductive metal. Insulative layers are preferably provided on the external electrodes, and located so as to insulate the first and second terminals from each other.

Abstract: A semiconductor apparatus includes a mount pad formed on a substrate and a bump formed on a semiconductor device. A plurality of needle-like or branch-like protrusions is formed on at least one of the mount pad and the bump. The plurality of protrusions of one of the mount pad and the bump engages with the other. The plurality of protrusions protrudes in directions crossing each other, or protrudes to random directions.

Abstract: An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The contact is particularly useful in integrated circuits which include high dielectric constant materials.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film and etching is stopped when barrier metal layers under the metal layer is exposed. Then, after forming spacers on the sidewalls of an upper conductive layer, the barrier metal layers (a barrier layer and an ohmic layer) are removed using the spacers as etching masks. Therefore, it is possible to prevent problems due to etch mask misalignment, such as 1) an etching gas of the metal layer permeating through the ohmic layer and 2) defects such as contact resistance changes that occur when spacers cover a contact hole even though the upper conductive layer does not completely cover that contact hole.

Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Abstract: A method for forming flip chip bumps or UBM for a high speed copper interconnect chip, and more particularly to a method for forming a flip chip bump or UBM of copper/nickel, copper/nickel/copper or etc. which are carried out by a subsequent process of electroless copper plating and electroless nickel plating on a copper I/O pad. According to the method, both of electroless copper and nickel plating methods are used for forming electroless copper/nickel bumps of a copper interconnect chip so that advantages of the electroless copper plating, i.e. excellent selectivity and adhering strength to the copper chip pad and an advantage of the electroless nickel plating, i.e. excellent plating rate can be achieved at the same time.

Abstract: In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A method of film processing comprises forming an integrated titanium/titanium nitride (Ti/TiN) film structure having an intermediate layer. The intermediate layer comprises species containing Si, and preferably containing Si and Ti, such as titanium silicide (TiSix), or TiSixOy, among others. The intermediate layer protects the underlying Ti film against chemical attack during subsequent TiN deposition using a titanium tetrachloride (TiCl4)-based chemistry. The method allows reliable Ti/TiN film integration to be achieved with excellent TiN step coverage. For example, the film structure can be used as an effective barrier layer in integrated circuit fabrication.

Abstract: A semiconductor device comprises a wiring in each of one or more wiring layers formed on a semiconductor substrate, and wiring sidewall layers which are formed on side edge portions of the wiring and which include fluorine-containing silicon oxide. It is possible to form an inter-wiring insulating film comprising fluorine-containing silicon oxide or Hydroxy Silsesquioxane on the outer surface of the wiring sidewall layers. Further, it is possible to form thermally diffused regions of fluorine into which fluorine is thermally diffused from the wiring sidewall layers in the inter-wiring insulating layer and near the interfaces with the wiring sidewall layers.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: To realize an ohmic electrode having practically satisfactory characteristics relative to GaAs semiconductors, first formed on an n+-type GaAs substrate are a Ni thin film with a thickness between 8 nm and 30 nm, an In thin film with a thickness between 2 nm and 6 nm and a Ge thin film with a thickness between 10 nm and 50 nm, sequentially. After that, the n+-type GaAs substrate having formed the Ni thin film, In thin film and Ge thin film is annealed at a temperature between 300 to 600° C. for a few seconds to minutes. As a result, the ohmic electrode has a multi-layered structure including an n++-type re-grown GaAs layer re-grown from the n+-type GaAs substrate, InGaAs layer and NiGe thin film. Alternatively, before the annealing, a thin film of a refractory metal or its compound, such as Nb thin film, with or without another thin film of a wiring metal, such as Au thin film, may be further formed on the Ge thin film.

Abstract: A monolithically integrated semiconductor circuit apparatus includes circuit elements disposed on a semiconductor substrate. The circuit elements include at least one semiconductor memory device, drive circuits, and a digital logic component monolithically integrated on the semiconductor substrate. A first contact-making plane is provided which is closer to a main surface of the semiconductor substrate than a penultimate contact-making plane, which is closer to the main surface of the semiconductor substrate than a last contact-making plane. The first, penultimate, and last interconnect patterns electrically interconnect the plurality of circuit elements. A protection device is formed at least in a partial region of the penultimate interconnect pattern. The protection device includes at least a fuse or an antifuse and is assigned to a redundancy activation for defective memory cells and memory cell groups in the semiconductor memory device.

Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

Abstract: A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.

Abstract: Formed on the semiconductor chip surface are electrode pads, on which electroless Ni plated bumps are formed. The electroless Ni plated bumps are arranged in at least two rows in parallel with the two sides of the semiconductor chip, opposing each other. Each electroless Ni bump is 5 &mgr;m or more in height and the surface is coated with Au plating as a metal film. The surface of the conductor leads is coated with Sn plating. The conductor leads and bumps are heated and pressed by a bonding tool to crate Au/Sn eutectic alloy junctions.

Abstract: A copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metallurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: Methods of forming a graded layer is disclosed. The graded layer transitions from one material to another material. The properties of these materials are chosen to optimize the interfaces on each side of the graded layer. Specifically, an improved transistor gate stack barrier layer may be formed by disposing an appropriate graded layer between a gate layer and an interconnect layer. In fact, the graded layer may obviate the use of the interconnect layer, as the top of the graded layer may include a highly conductive material. An improved integrated circuit interconnect structure may also be formed by grading the material composition of an interconnect layer.

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.

Abstract: Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.

Abstract: An integrated circuit chip (10) includes a substrate (12), a plurality of transistors (16) provided in the substrate (12), a circuit pattern (14) provided on a top surface of the substrate (12) and a metal layer (42) comprising at least two metals in substantially eutectic proportions provided on a bottom surface of the substrate, the bottom surface of the metal layer (42) being exposed. The integrated circuit chip (10) can be attached to a farther substrate, e.g., a housing, using automated attachment techniques. The chip (10) can be attached to the housing by picking up the integrated circuit chip (10) with the metal layer (42) provided on the bottom surface thereof and placing the integrated circuit chip (10) onto a housing so the bottom surface of the integrated circuit chip (10) faces the housing with the metal layer (42) there between; and then heating the metal layer (42) to a temperature above its eutectic temperature to melt the metal layer and attach the integrated circuit chip (10) to the housing.

Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIPOS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.

Abstract: An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.

Abstract: An article comprising a metal circuit and/or a heat-radiating metal plate formed on a ceramic substrate, wherein the metal circuit and/or the heat-radiating metal plate comprise either (1) the following first metal-second metal bonded product, wherein the first metal and the second metal are different, or (2) the following first metal-third metal-second metal bonded product, and wherein in (1) and (2), the first metal is bonded to the ceramic substrate; first metal: a metal selected from the group consisting of aluminum (Al), lead (Pb), platinum (Pt) and an alloy containing at least one of these metal components; second metal: a metal selected from the group consisting of copper (Cu), silver (Ag), gold (Au), aluminum (Al) and an alloy containing at least one of these metal components; and third metal: a metal selected from the group consisting of titanium (Ti), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W) and an alloy containing at least one of these metal components.

Abstract: A substrate for reducing electromagnetic emissions is provided. The substrate may include a plurality of ground layers, signal layers and power layers. All of the layers other than the ground layer are provided with a ground ring that may extend around the perimeter of the layer. The ground rings are electrically coupled together by ground stitching or vias that are randomly spaced. The random spacing of the ground stitching is based on the operating frequencies of the integrated circuit devices mounted on the substrate. Additional shielding may be provided by providing a cover assembly made of any conductive material that is coupled to the exposed ground rings on the uppermost and lowermost surfaces of the substrate. The cover assembly is coupled to the exposed ground rings in a randomized pattern. The device provides a virtual electrical ground cage in which the internal signal layers are totally enclosed, thereby reducing electromagnetic emissions.

Abstract: An object of the invention is to provide a light emitting diode which enables relatively easy fabrication of large-area displays and is applicable to thin, long life, low cost, full color displays too. The object is attained by a light emitting diode comprising a positive electrode, a negative electrode, an inorganic light emitting layer between the electrodes exhibiting at least electroluminescence, a high resistance inorganic electron transporting layer between the inorganic light emitting layer and the negative electrode, capable of blocking holes and having conduction paths for carrying electrons, and an inorganic hole transporting layer between the inorganic light emitting layer and the positive electrode, the inorganic hole transporting layer being a high resistance inorganic hole transporting layer capable of blocking electrons and having conduction paths for carrying holes.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the thermal expansion of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Abstract: The power semiconductor component has a semiconductor body which is electrically supplied through a contact clip. A solder ball connects the semiconductor body to the contact clip. The contact clip has a meandering electrical supply to a solder land, into which the solder ball is inserted.

Abstract: A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.

Abstract: Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes removing a predetermined portion of a first backside layer, opening chosen local areas with focused ion beam etching through at least the first backside layer, and exposing a desired node in a metal layer lower than the first backside layer with reactive ion etching. The method further includes removing the predetermined portion by performing reactive ion etching to a predetermined stop point. Alternatively, the first backside layer is mechanically polished to a predetermined thickness. Additionally, the method includes utilizing a high current ion beam during the focused ion beam etching.

Abstract: A semiconductor device comprising:a silicon substrate having a primary plane;an insulation film formed on the primary plane of the silicon substrate by subjecting the silicon substrate to thermal oxidation in an atmosphere of a gas of N.sub.2 O or a mixing gas of N.sub.2 O and O.sub.2 ; andan electrode formed on the insulation film and having nitrogen and a p-type dopant added therein.

Abstract: A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in t

Abstract: A composite conductor for contacting a semiconductor device chip. A durable substrate subassembly for a high power transistor switching modules. The substrate subassembly is durable because wire bonds to the semiconductor device electrodes are replaced with a soldered metal/ceramic composite conductor. The part of the composite conductor contacting the semiconductor device has a coefficient of thermal expansion close to that of the semiconductor device. The substrate in the substrate subassembly has automatic alignment features. The composite conductor also has automatic alignment features, along with stress relief features. Automatic alignment permits concurrent soldering of the chip to the substrate, and the composite conductor to the chip and to a terminal contact.