Abstract: An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.

Abstract: A wiring layer 17' of a semiconductor device is formed, at first, by forming a Cu--Ta film 15 by adding 0.5 weight % of Ta in Cu on a barrier metal layer, and then, by forming a cap metal layer on the film 15. The wiring layer 17' is then etched with a high temperature RIE method. After this, the wiring layer 17' is heat-treated at about 450 .degree. C. for about 120 minutes in a hydrogen reduction atmosphere. With this heat treatment, Ta is precipitated at the grain boundaries of Cu of the Cu--Ta layer 15. Since Ta does not tend to be alloyed with Cu easily and has low solid solubility in Cu crystal, Ta is precipitated at the grain boundaries of Cu by the above heat treatment. When Ta is precipitated at the grain boundaries of Cu such way, grain boundary diffusion is suppressed to generate less voids, so that the resistance to EM is improved.

Abstract: There is provided a method of fabricating a semiconductor including the steps, in this order, of (a) forming an interlayer insulating film on a semiconductor substrate, (b) forming a first TiN film on the interlayer insulating film by sputtering, (c) forming a hole throughout the interlayer insulating film to thereby cause the semiconductor substrate to appear, (d) forming a second TiN film over the first TiN film by chemical vapor deposition to thereby fill the hole with the second TiN film, and (e) removing the first and second TiN films except TiN filling the hole therewith. When a Ti or TiN film having a thickness sufficient to fill a contact hole or a through-hole therewith is to be formed by CVD even at low temperature, the this method prevents the Ti or TiN film from being cracked or peeled off.

Abstract: The semiconductor device manufacturing method includes the step of forming a second tungsten film on a first tungsten film, which is formed by using a reduction gas not-containing diborane, by using a gas containing the diborane, or forming the second tungsten film on the first tungsten film after the first tungsten film has been exposed to the gas containing the diborane.

Abstract: A metal bump structure constituted by forming a second metal layer on a first metal layer is used which meets the conditions that the first metal layer is not melted at the time of reflow heating for connecting a substrate with a semiconductor chip and the second metal layer is made of a metal producing no composition causing the reliability to deteriorate between the second metal layer and a solder portion formed on the substrate at the time of reflow heating for connecting the substrate with the semiconductor chip.

Abstract: In accordance with the present invention, an improved method and structure is provided for integrating polymer and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. Since the bond is typically weak between low-k materials such as polymers 18 and traditional dielectrics such as SiO.sub.2 22, the weak bonding may cause delamination or other problems during subsequent processing. The present invention increases yield and simplifies processing subsequent to application of the low-k material by providing an adhesion/protective layer 20 between the low-k material 18 and the intermetal dielectric 22. A preferred embodiment is a spun-on layer 20 of HSQ cured on a hotplate prior to application of the SiO.sub.2 intermetal dielectric.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: A nitride compound semiconductor light emitting element is made by stacking a metal layer made of one of elements: palladium (Pd), scandium (Sc), vanadium (V), zirconium (Zr), hafnium (Hf), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co) and copper (Cu), and another metal layer made of one of elements: titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W) and magnesium (Mg), to increase the adhesive strength of its electrodes with a semiconductor layer, reduce the contact resistance of the electrodes to improve the ohmic characteristics, and improve the external quantum efficiency by combination of thin-film metals with a transparent electrode.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: A bonding pad structure in accordance with the present invention is formed on a semiconductor substrate. The bonding pad structure comprises a buffer layer, a planarization layer, a conducting pad, and a passivation layer. The buffer layer is formed over the semiconductor substrate, and the planarization layer is thereafter formed on the buffer layer. The buffer layer is patterned and etched to shape a plurality of contact holes. The conducting pad is formed on the planarization layer and filled in the contact holes in order to mechanically interlock with the planarization layer. The passivation layer overlies peripherals of the conducting pad forming an overhang region therebetween. Moreover, the width of a portion of the overhang region close to a drawing direction may be enlarged so that the adhesion between the conducting pad and the passivation layer can be increased.

Abstract: A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-l

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: A process for metallizing semiconductor devices is provided, wherein a plurality of aluminum contacts is formed. The plurality of aluminum contacts is at least partially nitrided in a nitrogen-containing plasma at a temperature of less than about 350.degree. C. The aluminum nitride layer or cap is capable of eliminating aluminum corrosion without affecting the electrical properties of the aluminum contacts.

Abstract: A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that creates an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.

Abstract: An improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 and low dielectric constant materials by creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. A stabilizing layer is inserted between layers of low-k films. Since the thickness of problematic low-k materials remain less than the cracking threshold, many of the problems discussed above are alleviated. The stabilizing prevents the nucleation and propagation of micro cracks. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines.

Abstract: The invention provides a wire-bonding type semiconductor device including, a semiconductor chip, a plurality sets of electrode pads formed on the semiconductor chip, each set including a power supply electrode, at least one signal electrode pad and a gland electrode pad arranged in this order, a mount on which the semiconductor chip is placed, the mount being formed with the same number of extensions as the number of the gland electrode pads, the extension acting as gland leads, the same number of power supply leads as the number of the power supply electrode pads, the same number of signal leads as the number of the signal electrode pads, the power supply leads, the signal leads and the projections acting as gland leads being arranged in this order, and metal wires for connecting each of the power supply electrode pads, signal electrode pads and gland electrode pads to the power supply leads, the signal leads and the extensions, respectively, the metal wires being disposed substantially in parallel with one

Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.

Abstract: A semiconductor lead frame having an improved structure formed of plated layers is provided. The semiconductor lead frame has the structure of multi-plated layers in which a Ni plated layer, a Pd strike plated layer, and a Pd--X alloy plated layer are deposited on a substrate in the described order. In such a multi-plated layer structure, the Pd strike plated layer covers the porous surface of the Ni plated layer and decreases the surface roughness. Since the thickness of the outer Pd--X alloy plated layer can be maintained uniform due to the Pd strike plated layer, corrosion durability and bonding characteristics are enhanced, thus minimizing the generation and progress of cracks.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

Abstract: A three-dimensional polysilicon capacitor for use within integrated circuits and a method by which the three-dimensional polysilicon capacitor is formed. Formed upon a semiconductor substrate is a first polysilicon layer which has a series of apertures formed at least partially through the first polysilicon layer. A conformal insulator layer is then formed upon the first polysilicon layer and into the apertures within the first polysilicon layer. The conformal insulator layer has a series of apertures corresponding to the series of apertures within the first polysilicon layer. A second polysilicon layer is then formed upon the surface of the conformal insulator layer and filling the apertures within the conformal insulator layer. Optionally, the first polysilicon layer may be formed from a multi-coating stack comprising two polysilicon coatings separated by an metal silicide etch stop layer.

Abstract: A semiconductor laser includes (a) a semiconductor substrate of a first conductivity type on which is provided (b) a mesa stripe portion having a multilayer structure. The multilayer structure includes (b-1) an active layer provided on the semiconductor substrate. The laser also includes (c) a buried current blocking layer arranged on both sides of the mesa stripe portion, (d) a clad layer of a second conductivity type provided on the semiconductor substrate through at least a portion of the active layer, and (e) a contact layer of the second conductivity type provided on the clad layer. The contact layer includes a first contact layer contacting the clad layer and a second contact layer provided on the first contact layer. The first contact layer has an energy gap smaller than that of the clad layer and larger than that of the second contact layer. Preferably, the first contact layer is an InGaAsP semiconductor layer having an energy gap within the range of from 0.82 eV to 1.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti-Al-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: A lead frame for a semiconductor device includes a base layer which is coated by a protective coating. The protective coating includes a layer of nickel, over which is coated a layer of copper. The layer of copper is coated by a layer of silver over which is coated a layer of palladium. Protective coatings constructed in this way are bondable, solderable, oxidation resistant, corrosion resistant, free of lead (Pb), resistant to high temperatures, cost effective, and cosmetically acceptable. It is also possible to use a layer of tin or a tin alloy in place of the silver layer. It is possible to omit the nickel layer if the lead base layer is made of a ferrous material.

Abstract: An electronic device is formed by connecting a wiring plate and insulating plates mounting semiconductor chips to a base. A composite material plate, which is made by combining materials having different linear thermal expansion coefficients, is inserted between the base and the insulating plates through solders. The thickness ratio (h.sub.a /h.sub.b) of the materials of the composite material plate is selected in such a manner that strain in the solder between the base and the composite material plate is equal to the strain in the solder between the insulating plate and the composite material plate. In accordance with one embodiment of the invention, a single insulating plate is provided for mounting a plurality of semiconductor chips.

Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

Abstract: A leadframe for use in mounting and interconnecting an integrated circuit. A first or base metal layer of the leadframe comprises at least one of brass or other copper alloy. A second, conducting layer atop the base layer comprises at least one of aluminum or an aluminum alloy. A third, upper layer on the second layer comprises at least one of copper or a copper alloy. The first, second and third layers are formed into a multilayer clad strip, a portion of at least the third layer being selectively removed to expose a selected pattern of the second layer.

Abstract: This invention includes semiconductor devices including the heat sink with a slitted metal strip, such as copper, which is coiled or folded to produce an array of flexible flat fingers for mechanical, thermal and electrical contact with the silicon die, such as a power transistor. The use of a slitted metal strip instead of a bundle of wires makes fabrication of the flexible mount simpler and more economical. The flexible flat fingers are able to accommodate hot spots on the semiconductor device and change in thermal gradients as the device is operated.

Abstract: An improved solder-bonding structure is disclosed that is particularly suitable for soldering the components of hybrid ICs. The solder-bonding structure includes a conductor formed on a substrate. The conductor is formed from silver and platinum. A solder layer formed from a tin and silver solder is then formed on the conductor to couple an electronic element to the conductor. In preferred aspects of the invention, the platinum content in the conductor is in the range of approximately 0.7 to 1.0% by weight. The silver content in the solder layer is in the range of approximately 0.1 to 5.0% by weight.

Abstract: Lead frames completely surface-plated with palladium have a nickel-phosphorus or copper-tin layer between the base element, made for example of copper, and the palladium layer. Such lead frames exhibit good bondability and good solderability without tinning.

Abstract: In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: A multilayer conductive wire is formed of a plurality of conductive layers stacked upon each other, and has a slit shaped groove extending in the direction intersecting the direction of stress in at least one conductive layer. With the groove mating with a protrusion in another conductive layer or a protrusion in an insulating film layer, a sliding phenomenon between the layers due to the stress can be restrained, so that a multilayer conductive wire free from destruction due to the sliding phenomenon caused by the stress and without losing conductivity can be provided.

Abstract: A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and gate (16). The source (18) of the low voltage MOS transistor (12) is connected to the gate (16) of the high voltage transistor (14). The drain (22) of the low voltage MOS transistor (12)is connected to the source (20)of the high voltage transistor The low voltage MOS transistor (12) may have a silicon substrate and the substrate of the high voltage transistor (14)may comprise silicon, silicon carbide, or gallium arsenide.

Abstract: A light transmissive, electrically conductive oxide comprising tin and a Group II element is doped with a Group III element and with one or more of hydrogen or fluorine. The oxide may be deposited by sputtering at a temperature in the range from 25.degree. to 350.degree. C., or by chemical vapor deposition at temperatures in the range from 80.degree. to 400.degree. C.

Abstract: A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon is formed in the hole in the polysilicon layer. A thin oxide layer over the polysilicon layer is used for convenient end point detection during the formation of the polysilicon sidewall spacers. The sidewall spacer reduces the bore dimension of the hole in the polysilicon used for the mask for forming the contact hole. A hole is then etched in the thick oxide which is sloped and which has a bore dimension determined by the hole in the polysilicon which is reduced due to the sidewall spacer. The heavily-doped region, the contact hole, and the remaining polysilicon are coated with a barrier. The contact hole is then filled with a conductive material which also coats the barrier.

Abstract: A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

Abstract: An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer.

Abstract: A planarized multi-layer metal bonding pad. A first metal bonding pad layer (13) that defines a metal bonding pad is provided. A first dielectric layer (14) is provided with a multitude of vias (17) that covers the first metal bonding pad layer (13), thereby exposing portions of the first metal bonding pad layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal bonding pad layer (18) that further defines the metal bonding pad is deposited on the first dielectric layer (14) making electrical contact to the first metal bonding pad layer through the multitude of vias (17). Planarization of the second metal bonding pad layer (18) is achieved by having the second metal bonding pad layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Abstract: A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer has substantially the same grain size as the first aluminum.

Abstract: A semiconductor device having a GaAs substrate and an ohmic electrode. An electrode pad is on part of the ohmic electrode and on part of the GaAs substrate outside the ohmic electrode. The electrode pad includes a first platinum film, a titanium film, a second platinum film, and a gold film which are sequentially deposited on one another. The first platinum film is thinner than each of the titanium film, second platinum film and gold film.

Abstract: Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. Conductive material fills the at least one opening, and electrically connects the top and bottom bond pads. In one embodiment, the at least one opening is a plurality of conductive vias. In another embodiment, the at least one opening is a ring-like opening extending around the peripheral region. In yet another embodiment, the at least one opening is one or more elongated slit-like openings.

Abstract: A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a VIA hole. Filling a wiring conductor in the VIA hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.

Abstract: A semiconductor device comprises a semiconductor substrate, plural conductive lead circuit layers, one or more intermediate insulating layers interposed between the conductive lead circuit layers, and plural hole made in respective intermediate insulating layer. The hole has both a width larger than a width of the connection portion of the first conductive lead circuit layer positioned under the via and a depth that at a least a top face of the connection portion of the first conductive lead circuit layer is exposed, and a tungsten plug has a width layer than the width of the connection portion of the first conductive lead circuit layer, formed over at least the top face of the connection portion of the lower lead circuit layer 3. A gap between the conductive plug and the inner wall of the hole, is filled up with insulating material to form a flat surface on which the second conductive lead circuit layer is formed.