Abstract: A semiconductor device in which at least one IIL transistor is formed, the semiconductor device having, a base region (6) provided against a semiconductor substrate (1), a plurality of collector regions (9) formed in the base region (6), each of the collector regions (9) aligning in a direction parallel to a spreading surface of the semiconductor substrate (1), and a metal wiring having a plurality of contact portions (10), each of the contact portions being connected electrically to predetermined one of the collector regions (9), characterized in that, each of the contact portions of the metal wiring (10) is connected electrically to the collector region (9) corresponding thereto via a polysilicon cap (11) formed so as to cover the collector region (9).

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: A high frequency power MOS device (90) that is built by MOS technology having high speed switching capability. The device provides improved turn-on and turn-off capabilities by providing gate interconnects comprising substantially metallization, thereby reducing parasitic resistance and capacitance. The device may be fabricated by a MOS process relying upon a dual metallization layer (127, 133) for forming the interconnects. The dual metallization layer has substantially less resistivity than the conventional polysilicon and metallization layer interconnect.

Abstract: In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern.

Abstract: A method is provided for forming an improved landing pad with barrier of a semiconductor integrated circuit, and an integrated circuit formed according to the same. An opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a silicide layer disposed over a barrier layer which is disposed over a polysilicon layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. The barrier layer, formed as part of the landing pad, will provide for a uniform and high integrity barrier layer between the diffused region and an overlying aluminum contact to prevent junction spiking. A second dielectric having an opening therethrough is formed over the landing pad. A conductive contact, such as aluminum, is formed in the contact opening.

Abstract: A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide, removing unreacted palladium from the substrate, forming doped silicon on the palladium silicide and substrate, causing the silicon to be transported through the palladium silicide for recrystallizing on the substrate for forming epitaxially recrystallized silicon regions on the substrate and lifting the palladium silicide above the epitaxially recrystallized silicon regions for forming a silicided contact therefor, and removing the doped silicon from the substrate.

Abstract: In a semiconductor device, a layer of nitrogen doped polysilicon is applied to a gate oxide in turn provided on a semiconductor body, and then a silicide film is applied to the polysilicon layer. The nitrogen in the polysilicon layer inhibits growth of native oxide on the polysilicon layer prior to the application of silicide, and at subsequent high temperature processing steps, so that the problem of the silicide layer lifting from the polysilicon layer due to this native oxide growth is avoided during subsequent high temperature processing of the device.

Abstract: A three-dimensional polysilicon capacitor for use within integrated circuits and a method by which the three-dimensional polysilicon capacitor is formed. Formed upon a semiconductor substrate is a first polysilicon layer which has a series of apertures formed at least partially through the first polysilicon layer. A conformal insulator layer is then formed upon the first polysilicon layer and into the apertures within the first polysilicon layer. The conformal insulator layer has a series of apertures corresponding to the series of apertures within the first polysilicon layer. A second polysilicon layer is then formed upon the surface of the conformal insulator layer and filling the apertures within the conformal insulator layer. Optionally, the first polysilicon layer may be formed from a multi-coating stack comprising two polysilicon coatings separated by an metal silicide etch stop layer.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first insulating film on a semiconductor substrate, (b) forming gate electrodes on the first insulating film, the gate electrodes having a two-layered structure including a first conductive film and a second insulating film lying over the first conductive film, (c) forming a diffusion layer around the gate electrodes, (d) forming an insulating sidewall film around a sidewall of the gate electrodes, (e) covering a resultant with a third insulating film, (f) forming a contact hole between the gate electrodes in self-aligning fashion, (g) covering a resultant with a second conductive film, (h) covering a resultant with a fourth insulating film, (i) planarizing the fourth insulating film, (j) isotropically etching the planarized fourth insulating film to make a part of the second conductive film to appear, (k) covering a resultant with a third conductive film, and (l) etching the third conductive film, the fourt

Abstract: A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction.

Abstract: A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

Abstract: A bonding pad adapted for use with an Aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick Aluminum alloy bonding pad.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

Abstract: In a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer, a transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: In a semiconductor polycide resistive element having a first region of polysilicon of one conductivity type and second regions of polysilicon of opposite conductivity type, with silicide overlying the polysilicon but not the first region, the edges of the silicide are spaced apart from the boundaries between the opposite conductivity types.

Abstract: A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths and shallow source/drain junction depths was achieved. The method for fabricating the FET includes a conducting layer that is deposited and patterned over the source/drain areas of the FET. The sub-quarter micrometer channel length was achieved by reducing the channel opening formed in the conducting layer using sidewall spacer techniques. The conducting layer on the substrate and under the source/drain polysilicon layer also serves as an interface to the diffusing source/drain dopants, and shallow junctions are formed that are about 0.06 to 0.08 um depth. The conducting layer also serves as a low resistant ohmic contact to the source/drain areas.

Abstract: A lower-level conductor layer is formed in a surface of, on or over a semiconductor substrate. An interlayer insulator film is formed on the lower-level conductor layer. An upper-level conductor layer such as an interconnection layer of the semiconductor device is formed on the interlayer insulator film. A conductor plug is formed in a contact hole of the interlayer insulator film. The lower-level conductor layer and the upper-level conductor layer are electrically connected with each other through the conductor plug. A top part of the conductor plug protrudes from the interlayer insulator film. The upper-level conductor layer is contacted with a top face and a side face of the top part of the conductor plug. Both the contact resistance between the conductor contact and the upper-level conductor layer and the resistance of the upper-level conductor layer itself can be reduced without using a special equipment and a special process.

Abstract: In a CMOS-element-containing semiconductor device, the CMOS element comprises: a silicon substrate; an n-channel MOS element formed on the silicon substrate and including an n-type source/drain region, a gate oxide film and a gate electrode; a p-channel MOS element formed on the silicon substrate and including a p-type source/drain region, a gate oxide film and a gate electrode; and a gate wiring layer electrically interconnecting the gate electrode of the n-channel MOS element and the gate electrode of the p-channel MOS element with one another. At least one of the gate electrodes and the gate wiring layer include at least in part a metal silicide layer. The gate electrodes and the gate wiring layer contain impurities consisting of at least one of a III group dopant and a V group dopant in a total concentration of at most 3.times.10.sup.20 atoms cm.sup.-3.

Abstract: In a complementary MIS semiconductor device of a dual gate structure, an N-type polysilicon layer for an N-channel transistor and a P-type polysilicon layer for a P-channel transistor are formed on a gate oxide film and a field oxide film. A recessed portion is formed on the field oxide film in a region including a junctioning region of the N-type polysilicon layer and the P-type polysilicon layer such that thicknesses of the polysilicon layers are reduced. A continuous silicide layer is formed on the polysilicon layers. The silicide layer is thin in the recessed portion on the field oxide film and is thick on an active region of each of the transistors. In this semiconductor device of a dual gate type, it is possible to prevent impurities of the polysilicon layers of gate electrodes from being diffused in a transversal direction and restrain an increase in resistance value of each of the gate electrodes.

Abstract: This antifuse includes: a sublithographic conductive pattern (18); an antifuse material (24) overlying said sublithographic conductive pattern (18); and a conductive layer (26) overlying the antifuse material (24) to form a reduced area antifuse (10). Other devices, systems and methods are also disclosed.

Abstract: A p-type silicon substrate is provided at its main surface with n-type impurity regions with a space between each other. A gate electrode is formed on a region between the n-type impurity regions with a gate insulating film therebetween. A titanium silicide layer is formed in a region extending from a surface layer of the gate electrode to a surface layer of the n-type impurity region. The titanium silicide layer forms a local interconnection. A side wall insulating film remains on a side wall of the gate electrode on which the titanium silicide layer is not formed. Thereby, the semiconductor device can have a local interconnection which has high reliability and can be formed easily.

Abstract: A semiconductor device has a contact structure between two conductive layers capable of effectively preventing growth of an oxide film and diffusion of impurities between an impurity diffused region in a first one of the conductive layers and a polycrystalline silicon film (the second conductive layer) formed to be in contact with the impurity diffused region. The contact structure between the two conductive layers includes an n-type impurity diffused region 3 formed on a silicon substrate 1, an nitrided oxide film 4 formed to be in contact with the n-type impurity diffused region 3, and a polycrystalline silicon film 5a formed on the nitrided oxide film 4 and doped with impurities. Accordingly, growth of an oxide film and diffusion of impurities between the n-type impurity diffused region 3 and the polycrystalline silicon film 5a are also effectively prevented in a case where heat treatment at a high temperature is subsequently carried out in an oxygen atmosphere.

Abstract: The upper and lateral surfaces of a polycide electrode comprising a P.sup.+ -type polycrystalline silicon layer 6 and a tungsten silicide layer 13 are covered with silicon nitride films 9, 9A. Reduction of the boron concentration at the interface between the lower polycrystalline silicon layer and the upper tungsten silicide layer is suppressed.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850.degree. C.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A polycrystal silicon electrode and a side wall are formed in a method for manufacturing a semiconductor device. Thereafter, air is exhausted from a film forming chamber until a vacuum degree of 4.times.10.sup.-8 Torr. A mixing gas of N.sub.2 and argon (At) is introduced into this chamber with 60 sccm and a pressure within the chamber is set to 2.0 mTorr. A percentage of N.sub.2 to argon (Ar) in this mixing gas atmosphere is set to 10%. Direct current power 6 kW is applied to a titanium target having 99.998% in purity and 12 inches in length so that the titanium target is sputtered and formed as a titanium film including nitrogen. The titanium film is processed rapidly and thermally for 30 seconds at a temperature of 750 .degree. C. by using a xenon (Xe) arc lamp. Thus, a silicide film is uniformly formed selectively on a silicon substrate and the polycrystal silicon electrode.

Abstract: Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

Abstract: A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: A semiconductor device comprises a semiconductor layer including a source region, a drain region and a channel region provided on an insulating film. A gate insulating film separates the semiconductor layer from a gate electrode. A thickness of the channel region is smaller than a thickness of the source or drain region, and a level of an interface between the channel region and the insulating film is different from a level of an interface of the source or drain region and the insulating film. All the surfaces of the channel region, source region and drain region which face the gate electrode are on the same level.

Abstract: An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

Abstract: A semiconductor device includes a polycrystalline silicon layer formed on a silicon layer with an oxide film therebetween, an interlayer insulating layer formed to cover the surface of the silicon layer and the surface of the polycrystalline silicon layer, and a silicon plug layer formed in an embedded manner in a contact hole in the interlayer insulating layer to be directly connected to the surface of an end portion of the polycrystalline silicon layer and the surface of the silicon layer in the proximity of the end portion of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicon plug layer have the same type of conductivity. By this interconnection structure, the semiconductor device is improved in the patterning accuracy of the contact portion of a multilayer stacked interconnection. Furthermore, an ohmic contact between conductive interconnection layers can be realized with relatively simple manufacturing steps without occurrence of a voltage drop caused by a pn junction.

Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: A memory cell region is provided with a pair of driver transistors as well as a pair of access transistors. Each of the access transistors is formed of a field effect transistor having a gate electrode layer. An insulating layer is formed over the driver transistors and access transistors, and is provided with contact holes located within the memory cell region and reaching the gate electrode layers. Conductive layers are formed on the insulating layer, and are in contact with the gate electrode layers through the contact holes. Thereby, a memory cell structure of an SRAM has a small planar layout area and thus is suitable to high integration.

Abstract: A high frequency power MOS device (90) that is built by MOS technology having high speed switching capability. The device provides improved turn-on and turn-off capabilities by providing gate interconnects comprising substantially metallization, thereby reducing parasitic resistance and capacitance. The device may be fabricated by a MOS process relying upon a dual metallization layer (127, 133) for forming the interconnects. The dual metallization layer has substantially less resistivity than the conventional polysilicon and metallization layer interconnect.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer.The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

Abstract: An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.

Abstract: A semiconductor device comprises a silicon substrate, a gate electrode including a conductive layer formed on the silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering the conductive layer, a conductive region formed in the surface of the silicon substrate at its portion adjacent to the gate electrode, a second insulating layer formed so as to cover the gate electrode and the silicon substrate, a third insulating layer formed so as to cover the second insulating layer, a contact hole formed by etching to penetrate the third and second insulating layers and to reach the conductive region, and a wiring layer formed to cover the third insulating layer and having a contact part extending inside the contact hole, and electrically connect to the conductive region, the second insulating layer being made of a material having a selected ratio of an etching rate relative to an etching rate of a material of the first insulating

Abstract: A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.