Including Organic Insulating Material Between Metal Levels Patents (Class 257/759)
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Patent number: 7554200Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.Type: GrantFiled: September 1, 2004Date of Patent: June 30, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Tongbi Jiang
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Patent number: 7550788Abstract: A semiconductor device includes a lower electrode, an upper electrode, and a fuse element that connects the lower electrode and the upper electrode. The height of the fuse element is greater than the depth of focus of a laser beam to be irradiated. The diameter of the fuse element is smaller than the diffraction limit of the laser beam. Thus, in the present invention, a vertically long fuse element is used, so that it is possible to efficiently absorb the energy of the laser beam. It is possible to cut the fuse element by using an optical system having a small depth of focus, so that the damage imposed on a member located above or below the fuse element is very small. As a result, the fuse element can be without destructing the passivation film.Type: GrantFiled: January 9, 2007Date of Patent: June 23, 2009Assignee: Elpida Memory, Inc.Inventor: Sumio Ogawa
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Patent number: 7550824Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.Type: GrantFiled: August 31, 2004Date of Patent: June 23, 2009Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Paul A. Farrar, Arup Bhattacharyya
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Patent number: 7547971Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: August 12, 2005Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7544966Abstract: A three terminal electrical bistable device that includes a tri-layer composed of an electrically conductive mixed layer sandwiched between two layers of low conductivity organic material that is interposed between a top electrode and a bottom electrode. The conducting mixed layer serves as the middle electrode. The device includes two memory cells composed of electrode/organic layer/mixed layer, where the interfaces between the electrically conductive mixed layer and the low conductivity organic layer exhibit bistable behavior.Type: GrantFiled: December 1, 2004Date of Patent: June 9, 2009Assignee: The Regents of the University of CaliforniaInventors: Yang Yang, Liping Ma, Jun He
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Patent number: 7541679Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.Type: GrantFiled: October 11, 2005Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Edward C Cooney, III, John A Fitzsimmons, Jeffrey P Gambino, Stephen E Luce, Thomas L McDevitt, Lee M Nicholson, Anthony K Stamper
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Patent number: 7541646Abstract: A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.Type: GrantFiled: February 12, 2007Date of Patent: June 2, 2009Assignee: Mitsubishi Electric CorporationInventors: Hitoshi Nagata, Takao Sakamoto, Naoki Nakagawa
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Patent number: 7538434Abstract: A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.Type: GrantFiled: March 8, 2005Date of Patent: May 26, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Hung-Wen Su, Shau-Lin Shue
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Patent number: 7521381Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.Type: GrantFiled: November 28, 2001Date of Patent: April 21, 2009Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Yoshinobu Nakada, Hiroyuki Shiraki
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Semiconductor device having a refractory metal containing film and method for manufacturing the same
Patent number: 7521802Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.Type: GrantFiled: March 17, 2005Date of Patent: April 21, 2009Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Mari Watanabe -
Publication number: 20090096106Abstract: A method of forming a feature in a substrate comprising the steps of: forming a dielectric layer on a substrate; forming an antireflective coating over the dielectric layer; forming a photoresist pattern over the antireflective coating; etching the dielectric layer through the patterned photoresist; and removing the antireflective coating and the photoresist, wherein the antireflective coating is a film represented by the formula SivOwCxNuHyFz, wherein v+w+x+u+y+z=100%, v is from 1 to 35 atomic %, w is from 1 to 40 atomic %, x is from 5 to 80 atomic %, u is from 0 to 50 atomic %, y is from 10 to 50 atomic % and z is from 0 to 15 atomic %, wherein the antireflective coating is formed by the chemical vapor deposition of a composition comprising (1) at least one precursor selected from the group consisting of an organosilane, an organosiloxane, and an aminosilane; and (2) a hydrocarbon, and wherein the hydrocarbon is substantially not removed from the antireflective coating.Type: ApplicationFiled: October 2, 2008Publication date: April 16, 2009Applicant: Air Products and Chemicals, Inc.Inventors: Raymond Nicholas Vrtis, Mark Leonard O'Neill, Andrew David Johnson
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Patent number: 7518244Abstract: By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in different directions. As integrated circuits scale, importance of line to line capacitance in one plane increases. Thus, in some embodiments, the dielectric constant of the oriented dielectric may be lower in the plane that controls line to line capacitance.Type: GrantFiled: April 11, 2005Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Kevin O'Brien, David Gracias
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Patent number: 7518245Abstract: In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to expose another region of the conductive pad. The semiconductor device also includes a conductive contact extending through the opening. The conductive contact is electrically connected to the conductive pad. As a result, manufacturing cost for the semiconductor device may be reduced while manufacturing throughput may be improved.Type: GrantFiled: June 22, 2004Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Je-Min Park
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Patent number: 7514779Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 ?m. The reason is as follows. If the diameter of the mesh hole is less than 75 ?m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 ?m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 ?m. The reason is as follows. If the distance is less than 100 ?m, the solid layer cannot function. If the distance exceeds 2000 ?m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.Type: GrantFiled: December 31, 2002Date of Patent: April 7, 2009Assignee: Ibiden Co., Ltd.Inventors: Naohiro Hirose, Honjin En
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Patent number: 7511296Abstract: An organic semiconductor device is provided which includes an organic semiconductor layer and an insulating layer. The insulating layer is made of a cured material formed from a composition containing a resin and a crosslinking agent. The resin contains an organic resin having a hydroxyl group. The crosslinking agent contains a compound having at least two crosslinking groups. At least one of the crosslinking groups is a methylol group or an NH group. The composition contains the crosslinking agent in the range of 15 to 45 percent by weight relative to 100 parts by weight in total of the resin and the crosslinking agent.Type: GrantFiled: March 14, 2006Date of Patent: March 31, 2009Assignee: Canon Kabushiki KaishaInventors: Tomonari Nakayama, Toshinobu Ohnishi, Daisuke Miura
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Patent number: 7504699Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.Type: GrantFiled: November 21, 2000Date of Patent: March 17, 2009Assignee: George Tech Research CorporationInventors: Paul A. Kohl, Qiang Zhao, Sue Ann Bidstrup Allen
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Patent number: 7504719Abstract: The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in facture toughness, dielectric constant, adhesion and processability, among other characteristics. The present invention is directed to a multilayer printed circuit board comprising a substrate board, a resin insulating layer formed on said board and a conductor circuit constructed on said resin insulating layer, wherein said resin insulating layer comprises a polyolefin resin.Type: GrantFiled: July 26, 2005Date of Patent: March 17, 2009Assignee: Ibiden Co., Ltd.Inventors: Honchin En, Masayuki Hayashi, Dongdong Wang, Kenichi Shimada, Motoo Asai, Koji Sekine, Tohru Nakai, Shinichiro Ichikawa, Yukihiko Toyoda
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Patent number: 7504727Abstract: Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features.Type: GrantFiled: May 14, 2004Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Timothy J. Dalton
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Patent number: 7504709Abstract: An electronic device including: a pair of electrodes; an organic semiconductor layer; and an organic film formed of organic compounds including nonconjugated organic compounds coupled to at least one of surfaces of the pair of electrodes.Type: GrantFiled: August 23, 2005Date of Patent: March 17, 2009Assignee: Seiko Epson CorporationInventors: Takashi Masuda, Hiroshi Takiguchi
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Patent number: 7489038Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.Type: GrantFiled: September 7, 2005Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette A. Awad, Kai D. Feng
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Patent number: 7485569Abstract: A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the via hole of the insulating layer. In addition, a method of fabricating a printed circuit board including embedded chips is provided.Type: GrantFiled: May 24, 2005Date of Patent: February 3, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Chang Sup Ryu, Doo Hwan Lee, Jin Yong Ahn, Myung Sam Kang, Suk Hyeon Cho
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Patent number: 7485915Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.Type: GrantFiled: May 5, 2006Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
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Patent number: 7485964Abstract: A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. Thereupon, thermodynamic conditions are changed to ambient wherein carbon dioxide escapes from the pores and is replaced with air.Type: GrantFiled: April 6, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: John M. Cotte, Kenneth John McCullough, Wayne Martin Moreau, Kevin Petrarca, John P. Simons, Charles J. Taft, Richard Volant
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Patent number: 7482624Abstract: In an organic electronic circuit, particularly a memory circuit with an organic ferroelectric or electret material the active material comprises fluorine atoms and consists of various organic materials. The active material is located between a first electrode and a second electrode. A cell with a capacitor-like structure is defined in the active material and can be accessed for an addressing operation via the first and the second electrode. At least one of these electrodes comprises a layer of chemically modified gold. In a passive matrix-addressable electronic device, particularly a ferroelectric or electret memory device, circuits of this kind with the active material as a ferroelectric or electret memory material form the elements of a matrix-addressable array and define the memory cells provided between first and second set of addressing electrodes. At least the electrodes of at least one of the sets then comprise at least a layer of gold.Type: GrantFiled: July 21, 2005Date of Patent: January 27, 2009Assignee: Thin Film Electronics AsaInventors: Rickard Liljedahl, Mats Sandberg, Göran Gustafsson, Hans G. Gudesen
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Patent number: 7479671Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.Type: GrantFiled: August 29, 2006Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Chung Hon Lam, Alejandro Gabriel Schrott
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Patent number: 7474002Abstract: In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to provide a method which smoothing surface can be achieved without a polishing treatment by CMP method or a smoothing process by depositing a SOG film, a substrate material is not chosen, and the smoothing is simple and easy. In the semiconductor device in which a plurality of different layers are formed, smoothing surface can be achieved without the polishing treatment by the CMP method or the smoothing process by depositing the SOG film to a dielectric film formed on a dielectric film and a wring (electrode) or a semiconductor layer in a manner that an aperture portion is formed in the dielectric film, the wring (electrode) or the semiconductor layer is formed in the aperture portion.Type: GrantFiled: October 17, 2002Date of Patent: January 6, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akira Ishikawa
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Patent number: 7470988Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: November 24, 2004Date of Patent: December 30, 2008Assignee: MEGICA CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 7466028Abstract: A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.Type: GrantFiled: October 16, 2007Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Hung-Jung Tu, Weng-Jin Wu
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Patent number: 7465656Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.Type: GrantFiled: June 1, 2006Date of Patent: December 16, 2008Assignee: Panasonic CorporationInventor: Masaki Tamaru
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Patent number: 7462900Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.Type: GrantFiled: February 28, 2008Date of Patent: December 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Horii Hideki, Bong-Jin Kuh, Yong-Ho Ha, Jeong-hee Park, Ji-Hye Yi
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Patent number: 7459389Abstract: A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.Type: GrantFiled: March 28, 2006Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventor: Anthony K. Stamper
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Patent number: 7459761Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.Type: GrantFiled: March 29, 2005Date of Patent: December 2, 2008Assignee: Megica CorporationInventor: Mou-Shiung Lin
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Publication number: 20080290521Abstract: In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR1)4 or R2nSi(OR3)4-n wherein R1s, R2(s) and R3(s) may be the same or different when a plurality of them are contained in the molecule and each independently represents a linear or branched C1-4 alkyl group in the presence of a hydrophilic basic catalyst and a hydrophobic basic catalyst is used for a conventional porous-film forming composition.Type: ApplicationFiled: February 12, 2008Publication date: November 27, 2008Inventors: Yoshitaka Hamada, Fujio Yagihashi, Takeshi Asano, Hideo Nakagawa, Masaru Sasago
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Publication number: 20080290522Abstract: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum.Type: ApplicationFiled: July 28, 2008Publication date: November 27, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Sadayuki Ohnishi, Kouichi Owto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
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Publication number: 20080284032Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.Type: ApplicationFiled: August 6, 2008Publication date: November 20, 2008Applicant: MEGICA CORPORATIONInventor: Mou-Shiung Lin
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Patent number: 7452802Abstract: Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.Type: GrantFiled: January 7, 2005Date of Patent: November 18, 2008Assignee: MangnaChip Semiconductor, Ltd.Inventor: Ihl Hyun Cho
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Publication number: 20080277796Abstract: A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.Type: ApplicationFiled: July 25, 2008Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen M. Gates, Robert D. Miller
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Patent number: 7449408Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.Type: GrantFiled: June 8, 2004Date of Patent: November 11, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Muranaka, Ryoji Nomura, Takeshi Shichi, Tatsuya Arao, Masahiro Katayama
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Patent number: 7446418Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.Type: GrantFiled: June 2, 2005Date of Patent: November 4, 2008Assignee: Fujitsu LimitedInventor: Kenichi Watanabe
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Publication number: 20080251926Abstract: An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas.Type: ApplicationFiled: February 14, 2006Publication date: October 16, 2008Applicant: NEC CorporationInventors: Munehiro Tada, Tsuneo Takeuchi, Yoshihiro Hayashi
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Patent number: 7436064Abstract: Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the metal pad, applying a beam, wherein the beam ablates the first material in an ablation window so that the ablation window includes at least a portion of an edge of the metal pad, and disposing a second electrode over the first material and over the ablation window so that the second electrode is in electrical contact with the at least a portion of an edge of the metal pad.Type: GrantFiled: April 26, 2006Date of Patent: October 14, 2008Assignee: Osram Opto Semiconductors GmbHInventors: Wen Han Lau, Ian Stephen Millard
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Publication number: 20080244902Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: Kim J. Blackwell, Frank D. Egitto, John M. Lauffer, Voya R. Markovich
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Publication number: 20080246154Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.Type: ApplicationFiled: June 13, 2008Publication date: October 9, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Publication number: 20080246153Abstract: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R1Si(OR2)3, (2): Si(OR3)4, (3): (R4)2Si(OR5)2, and (4): R6b(R7O)3-bSi—(R10)d—Si(OR8)3-cR9c.Type: ApplicationFiled: June 9, 2008Publication date: October 9, 2008Applicant: JSR CORPORATIONInventors: Hajime TSUCHIYA, Hiromi Egawa, Terukazu Kokubo, Atsushi Shiota
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Patent number: 7429793Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.Type: GrantFiled: September 22, 2006Date of Patent: September 30, 2008Assignee: Sony CorporationInventor: Osamu Yamagata
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Patent number: 7425764Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 17, 2007Date of Patent: September 16, 2008Inventor: Mou-Shiung Lin
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Patent number: 7425735Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.Type: GrantFiled: January 26, 2007Date of Patent: September 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Hee Park, Ju-Chul Park, Jun-Soo Bae, Bong-Jin Kuh, Yong-Ho Ha
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Patent number: 7423300Abstract: A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.Type: GrantFiled: May 24, 2006Date of Patent: September 9, 2008Assignee: Macronix International Co., Ltd.Inventors: Hsiang-Lan Lung, Rich Liu, Yi-Chou Chen, Shih-Hung Chen
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Patent number: 7422975Abstract: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.Type: GrantFiled: August 18, 2005Date of Patent: September 9, 2008Assignees: Sony Corporation, Sony Electronics Inc.Inventors: Takeshi Nogami, Kensaku Ida
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Patent number: 7423346Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: September 9, 2004Date of Patent: September 9, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou