Including Organic Insulating Material Between Metal Levels Patents (Class 257/759)
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Patent number: 7420279Abstract: An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond therein. The proportion of Si—CH2 bond (1360 cm?1) to Si—CH3 bond (1270 cm?1) in the insulating film is preferably in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum. The insulating film according to the present invention has higher ashing tolerance and improved adhesion to SiO2 film, when compared with the conventional SiOCH film which only has CH3 group.Type: GrantFiled: June 28, 2006Date of Patent: September 2, 2008Assignee: NEC Electronics CorporationInventors: Sadayuki Ohnishi, Kouichi Ohto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
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Patent number: 7420276Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.Type: GrantFiled: February 20, 2004Date of Patent: September 2, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Publication number: 20080203392Abstract: A display substrate includes a base substrate having a display area and a peripheral area which surrounds the display area, a pixel electrode formed on the display area, a pad part formed on the peripheral area, an adhesion part formed on the peripheral area and having a plurality of holes formed in an area adjacent to the pad part on the peripheral area and a conductive adhesion member formed on the pad part and the adhesion part to make electrical contact with the pad part and a terminal of an integrated circuit.Type: ApplicationFiled: February 22, 2008Publication date: August 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Hyun-Young KIM, Kwan-Wook JUNG, Seung-Gyu TAE
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Publication number: 20080203574Abstract: To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. where, R1, R2, R3, and R4 may be the same or different and at least one of them represents a functional group containing any of a hydrocarbon and an unsaturated hydrocarbon.Type: ApplicationFiled: February 26, 2008Publication date: August 28, 2008Applicant: FUJITSU LIMITEDInventors: Yasushi KOBAYASHI, Yoshihiro NAKATA, Shirou OZAKI
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Patent number: 7417326Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.Type: GrantFiled: March 14, 2006Date of Patent: August 26, 2008Assignee: Fujitsu LimitedInventors: Masamitsu Ikumo, Hiroyuki Yoda, Eiji Watanabe
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Patent number: 7413978Abstract: A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, electrically connecting the first conductive layer and the second conductive layer; wherein a reinforcement material is adhered to a vicinity of a root of the columnar structure.Type: GrantFiled: July 8, 2005Date of Patent: August 19, 2008Assignee: Seiko Epson CorporationInventor: Hideki Tanaka
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Publication number: 20080191354Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.Type: ApplicationFiled: April 10, 2008Publication date: August 14, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
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Publication number: 20080191353Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.Type: ApplicationFiled: April 10, 2008Publication date: August 14, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
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Patent number: 7408260Abstract: A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying the first surface of the microelectronic element, and conductive protrusions overlying the compliant layer and projecting away from the first surface of the microelectronic element, wherein the conductive protrusions are electrically interconnected with the contacts of the microelectronic element. The conductive protrusions are movable relative to said microelectronic element.Type: GrantFiled: July 14, 2006Date of Patent: August 5, 2008Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, Konstantine Karavakis
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Patent number: 7402513Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.Type: GrantFiled: January 12, 2005Date of Patent: July 22, 2008Assignee: Sharp Kabushiki KaishaInventors: Takanori Sonoda, Kazumasa Mitsumune, Kenichiroh Abe, Yushi Inoue, Tsukasa Doi
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Patent number: 7402846Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: October 20, 2005Date of Patent: July 22, 2008Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Patent number: 7397135Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 16, 2007Date of Patent: July 8, 2008Inventor: Mou-Shiung Lin
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Patent number: 7394156Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: GrantFiled: January 25, 2005Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Patent number: 7391114Abstract: A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.Type: GrantFiled: February 1, 2005Date of Patent: June 24, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadaaki Mimura, Tsuyoshi Hamatani, Atuhito Mizutani, Kenji Ueda
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Publication number: 20080142981Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: ApplicationFiled: February 25, 2008Publication date: June 19, 2008Inventor: Mou-Shiung Lin
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Publication number: 20080142979Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 18, 2008Publication date: June 19, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080142978Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: June 19, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080142980Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: ApplicationFiled: February 25, 2008Publication date: June 19, 2008Inventor: Mou-Shiung Lin
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Patent number: 7388292Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 27, 2007Date of Patent: June 17, 2008Inventor: Mou-Shiung Lin
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Patent number: 7388291Abstract: A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.Type: GrantFiled: February 24, 2005Date of Patent: June 17, 2008Assignee: NEC Electronics CorporationInventors: Tetsuya Kurokawa, Koji Arita
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Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
Patent number: 7384866Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.Type: GrantFiled: March 31, 2005Date of Patent: June 10, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo -
Patent number: 7385241Abstract: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.Type: GrantFiled: December 28, 2005Date of Patent: June 10, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Chee Hong Choi
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Patent number: 7385291Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: July 27, 2007Date of Patent: June 10, 2008Inventor: Mou-Shiung Lin
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Patent number: 7385292Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 27, 2007Date of Patent: June 10, 2008Inventor: Mou-Shiung Lin
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Publication number: 20080128911Abstract: A semiconductor package includes: a build-up wiring structure in which an insulating layer formed from a resin and a wiring layer formed from a conductive plating layer are stacked one on top of the other; a fine-wiring structure which is formed by patterning a conductive foil on a resin tape to which the conductive foil is attached, and includes a wiring layer that is finer than the wiring layer of the build-up wiring structure; and a junction layer which is formed from a thermoplastic resin and interposed between the build-up wiring structure and the fine-wiring structure, thereby bonding the structures together.Type: ApplicationFiled: November 13, 2007Publication date: June 5, 2008Inventor: Toshinori Koyama
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Patent number: 7382058Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 27, 2007Date of Patent: June 3, 2008Inventor: Mou-Shiung Lin
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Publication number: 20080122098Abstract: A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.Type: ApplicationFiled: December 12, 2007Publication date: May 29, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Minori Kajimoto, Mitsuhiro Noguchi, Akira Goda
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Publication number: 20080122099Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: May 29, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 7378740Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.Type: GrantFiled: August 2, 2005Date of Patent: May 27, 2008Assignee: United Microelectronics Corp.Inventors: Tri-Rung Yew, Yimin Huang, Water Lur, Shih-Wei Sun
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Patent number: 7378738Abstract: A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method.Type: GrantFiled: September 2, 2003Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Timothy A. Brunner, Matthew E. Colburn, Elbert Huang, Muthumanickam Sankarapandian
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Publication number: 20080116579Abstract: A method of manufacturing a multilevel interconnect structure using a screen printing method is disclosed. In the multilevel interconnect structure, an interlayer insulating film having a through hole with a conductive bump therein, and a second interconnect line are stacked on a substrate with a first interconnect line formed thereon. The first interconnect line is electrically connected to the second interconnect line via the conductive bump. The method includes a step of forming a first region of the interlayer insulating film on the substrate with the first interconnect line formed thereon, the first region including a part of a peripheral wall of the through hole; a step of forming a second region of the interlayer insulating film on the substrate with the first region formed thereon, the second region including a remaining part of the peripheral wall of the through hole; and a step of forming the conductive bump.Type: ApplicationFiled: October 30, 2007Publication date: May 22, 2008Inventor: Mayuka ARAUMI
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Patent number: 7372143Abstract: A via is formed in a printed circuit board to penetrate through an insulating layer. A guard pattern, made of an electrically-conductive material, extends on the front surface of the insulating layer along a circle concentric with the via. An electrically-conductive body extends from the guard pattern in the insulating layer along an imaginary cylinder concentric with the via. The guard pattern of the printed circuit board serves to control the characteristic impedance of the via at the front surface of the insulating layer. The electrically-conductive body contributes to a better control of the characteristic impedance of the via. The via is allowed to reliably enjoy a better impedance matching than ever. Noise can sufficiently be suppressed in electric signals running through the via.Type: GrantFiled: June 14, 2005Date of Patent: May 13, 2008Assignee: Fujitsu LimitedInventors: Naoki Nakamura, Midori Kobayashi
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Patent number: 7372154Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: December 1, 2004Date of Patent: May 13, 2008Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Patent number: 7372085Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: September 19, 2005Date of Patent: May 13, 2008Inventor: Mou-Shiung Lin
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Patent number: 7372155Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: May 18, 2005Date of Patent: May 13, 2008Inventor: Mou-Shiung Lin
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Publication number: 20080093743Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Haining Yang, Wai-Kin Li
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Patent number: 7361992Abstract: After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stopper 5 which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film 4 which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal 10.Type: GrantFiled: September 22, 2003Date of Patent: April 22, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Naoteru Matsubara, Kazunori Fujita
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Patent number: 7361991Abstract: A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectric and the optional interconnect vias located underneath. The lines and the lateral gap between them are straddled on top by a cap layer so that a closed air gap is formed. Several embodiments of this structure and methods to fabricate the same are also described.Type: GrantFiled: September 19, 2003Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Katherine L Saenger, Maheswaran Surendra, Anna Dorothy Karecki, legal representative, Satya V Nitta, Sampath Purushothaman, Matthew E Colburn, Timothy J Dalton, Elbert Huang, Simon M Karecki
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Patent number: 7358170Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.Type: GrantFiled: June 9, 2005Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventor: Chandra Tiwari
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Patent number: 7358610Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: July 27, 2007Date of Patent: April 15, 2008Inventor: Mou-Shiung Lin
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Patent number: 7355255Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: GrantFiled: February 26, 2007Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue E. Crank, Thomas D. Bonifield, Homi C. Mogul
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Publication number: 20080079164Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.Type: ApplicationFiled: October 2, 2007Publication date: April 3, 2008Applicant: NEC Electronics CorporationInventors: Yoichiro KURITA, Koji Soejima, Masaya Kawano
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Publication number: 20080079163Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: October 2, 2007Publication date: April 3, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Patent number: 7352061Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.Type: GrantFiled: May 20, 2005Date of Patent: April 1, 2008Assignee: Intel CorporationInventors: Mitul B. Modi, Patricia A. Brusso, Ruben Cadena, Carolyn R. McCormick, Sankara J. Subramanian
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Patent number: 7352065Abstract: A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer, and depositing a third layer comprising a medium-k dielectric barrier on the second layer.Type: GrantFiled: September 9, 2005Date of Patent: April 1, 2008Assignee: Nanodynamics, Inc.Inventor: Benjamin F. Dorfman
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Patent number: 7348593Abstract: An organic thin film transistor (OTFT) having an adhesive layer and a method of fabricating the same. The OTFT includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode and on remaining exposed portions of the substrate, an adhesive layer formed on the gate insulating layer, source/drain electrodes formed on the adhesive layer, and a semiconductor layer formed on the source/drain electrodes and on the adhesive layer. The gate insulating layer and the semiconductor layer are organic, the adhesive layer providing adhesion between the source/drain electrodes and the gate insulating film while preventing gate leakage current while also improving contact resistance.Type: GrantFiled: August 1, 2005Date of Patent: March 25, 2008Assignee: Samsung SDI Co., Ltd.Inventors: Jae-Bon Koo, Min-Chul Suh
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Patent number: 7345303Abstract: A novel barrier layer which protects electronic devices from adverse environmental effects such as exposure to light, especially white light, is described. The barrier layer comprises a copolymer having an acrylate unit and an acrylate unit with a pendant dye group. Also disclosed are processes for producing such electronic devices.Type: GrantFiled: December 22, 2005Date of Patent: March 18, 2008Assignee: Xerox CorporationInventors: Mihaela Maria Birau, Yiliang Wu, Beng S. Ong
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Patent number: 7342314Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.Type: GrantFiled: June 10, 2004Date of Patent: March 11, 2008Assignee: Infineon Technologies AGInventors: Jens Bachmann, Klaus Goller, Dirk Grueneberg, Reiner Schwab
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Patent number: 7338884Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.Type: GrantFiled: November 29, 2004Date of Patent: March 4, 2008Assignee: NEC CorporationInventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
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Patent number: 7335992Abstract: The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer.Type: GrantFiled: March 28, 2005Date of Patent: February 26, 2008Assignee: NEC Electronics CorporationInventor: Kunio Anzai