Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

Abstract: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.

Abstract: A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a second conductive layer, a second insulating layer, a tubular semiconductor pillar, an insulating film and an occlusion film. The second conductive layer is provided on the stacked body. The second insulating layer is provided on the second conductive layer. The tubular semiconductor pillar is provided in such a manner as to pass through the second insulating layer, the second conductive layer and the stacked body. The insulating film is provided between the semiconductor pillar, and the second insulating layer, the second conductive layer and the stacked body. The occlusion film occludes the tube in a lower portion of the portion passing through the second insulating layer in the semiconductor pillar. The tube below the occlusion film in the semiconductor pillar is an air gap.

Abstract: A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

Abstract: A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer.

Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of Zrx Hfy Sn1-x-y O2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Abstract: Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.

Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.

Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: An electrical power substrate comprises a metallic body at least one surface of the body having a coating generated by plasma electrolytic oxidation (PEO). The coating includes a dense hard layer adjacent the said surface of the metallic body, and a porous outer layer. Electrically conductive elements are attached to the said coating.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.

Abstract: A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.

Abstract: A semiconductor device includes a substrate, an element formed on the substrate, a nitride film formed on the substrate, a anti-peel film formed on the nitride film, and a molded resin covering the anti-peel film and the element. The anti-peel film has residual compressive stress.

Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.

Abstract: A semiconductor device of this invention has a copper wiring layer, of which a layer, to which a composition including at least one substance selected from the group consisting of ammonia and organic bases is applied, and a silicon-containing insulating film are sequentially superimposed on the copper wiring layer. Accordingly, semiconductor devices having insulating layers which adheres well to the copper serving as the wiring material can be obtained.

Abstract: A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.

Abstract: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure includes a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

Abstract: A semiconductor storage device includes a memory cell transistor and a selective transistor formed on a semiconductor substrate, a first interlayer insulating film which is formed on the semiconductor substrate, an insulating layer formed by use of a material higher in dielectric constant than the first interlayer insulating film, a contact plug which penetrates the insulating layer and the first interlayer insulating film and which is electrically connected to a drain of the selective transistor, and a bit line which is in contact with the contact plug. A partial region in the bottom surface of the bit line is located lower than the upper surface of the contact plug, and is in contact with the surface of the insulating layer, and the partial region is also in contact with the side surface of the contact plug.

Abstract: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.

Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Abstract: A MOS transistor includes an etch stop layer presenting a density of less than a determined threshold value, below which the material of said stop layer is permeable to molecules of dihydrogen and/or water. The material may comprise a nitride. A material used for the etch stop layer preferably has a density value of less than about 2.4 g/cm3.

Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.

Abstract: A semiconductor device includes a substrate; an alignment mark formed on the substrate and composed of a metal film; a cover insulating film formed on the alignment mark and covering an entire surface of the alignment mark; and a polyimide film formed on the cover insulating film, and having an opening, which is opened on the alignment mark and has an end face aligning with an end face of the alignment mark, in plan view.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.

Abstract: Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.

Abstract: An interconnection is formed on an object having a step by a screen printing method. The interconnection is formed by printing it on a substrate having an upper stage surface and a lower stage surface. A multilayer interconnection structure having a plurality of layers which are stacked is formed by repeatedly performing a process of printing and drying an interconnection pattern on the lower stage surface. Then, when the height of the multilayer interconnection structure approaches the height of the upper stage surface, an interconnection pattern of the uppermost layer is printed on the multilayer interconnection structure to extend onto the upper stage surface. Because the interconnection pattern of the uppermost layer is printed in a smaller step, the print characteristic is good. Thus, by the printing, the interconnection structure is formed which has a narrow interconnection width and surely connects the upper surface and the lower surface in a larger step than the interconnection width.

Abstract: A semiconductor device is manufactured by forming a first reinforcing insulating film and a first sacrificial interlayer. A first trench is formed and then filled with an interconnect covered with a cap metal. First and second sacrificial barrier dielectrics are formed, and the second sacrificial interlayer and the sacrificial barrier dielectric are selectively removed to form a hole exposing the cap metal. A conductive via connects the interconnect by forming a conductor in the hole, and a second cap metal covers the via. The interconnect exposes the via by selectively removing the sacrificial interlayers and dielectric. An insulating film covers the side wall and the upper portion of the interconnect, and the side wall of the conductive via which is connected to the interconnect from the side wall of the interconnect through the side wall of the via. An air-gap is provided in the insulating film.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.