Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines, where forming the dielectric layer after the conductive lines are formed mitigates damage to the dielectric layer, such as by not subjecting the dielectric layer to etching. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material. At least one of the substantially undamaged dielectric layer or the air gap serves to reduce parasitic capacitance within the semiconductor arrangement, which improves performance.

Abstract: Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract: An anisotropic conductive film composition for bonding an electronic device may include a hydrogenated bisphenol A epoxy monomer represented by Formula 1 or a hydrogenated bisphenol A epoxy oligomer represented by Formula 2: where n may be an integer from 1 to about 50.

Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as platinum, gold, silver and palladium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.

Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.

Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.

Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.

Abstract: A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: An image reading apparatus, an image information verification apparatus, an image reading method, an image information verification method, and an image reading program are disclosed. The image reading apparatus includes an image acquisition unit for acquiring an image from an image reading unit for reading the image formed on a medium, a medium description receiving unit for receiving a medium description provided by a medium description acquisition unit for acquiring the medium description of the medium, a set generating unit for generating a set of information about the image and information about the medium description, and a set unique value acquisition unit for acquiring a set unique value about the set.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: According to one embodiment, a method for forming a semiconductor device includes: forming a first underlayer film that contains a first atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals; forming, on the first underlayer film, a second underlayer film that contains a second atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals, the second atom being an atom not contained in the first underlayer film; and forming, on the second underlayer film, a silicon oxide film by a CVD or ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group, and an amino group, or a silicon source of a siloxane system.

Abstract: A method of manufacturing a solid electrolytic capacitor includes the steps of forming an anode element by sintering powders of a valve metal, washing the anode element with a first wash solution, forming a dielectric film on the anode element after the washing step, and forming a solid electrolytic layer on the dielectric film. The first wash solution is an aqueous solution containing ammonia and hydrogen peroxide.

Abstract: In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first conductive layer, and a third conductive layer introduced over the second conductive layer. One of the first conductive layer, the second conductive layer, and the third conductive layer comprises titanium-niobium (Ti—Nb).

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second metal layer and patterned to form a mask. The second metal layer is etched. The mask is then removed and the first metal layer is patterned with the second metal layer acting as mask for the first metal layer.

Abstract: A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer.

Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

Abstract: A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operating regions, and the element isolating region is etched to a shallower depth than a thickness of the semiconductor thin film, and is a thinner region than the plurality of discrete operating regions.

Abstract: A display device includes a plurality of thin-film transistors formed on a substrate on which a display area is formed. The display device also includes a gate electrode, a gate insulating film formed so as to cover the gate electrode, an semiconductor layer in an island shape formed on an upper surface of the gate insulating film so as to superimpose the gate electrode without protruding from the gate electrode when viewed planarly, an insulating film formed so as to cover the semiconductor layer, and a pair of electrodes electrically connected to the semiconductor layer respectively through a pair of through holes that are formed at the insulating film. The semiconductor layer is formed by sequentially laminating a crystalline semiconductor layer and an amorphous semiconductor layer. The pair of electrodes is respectively formed by sequentially laminating a semiconductor layer doped with impurities and a metal layer.

Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.

Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material. Resulting semiconductor device structures are also disclosed, as are compositions used to form the semiconductor device structures.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.

Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.

Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Abstract: An electronic apparatus is provided that has a core, an electronic circuit in the core and a lid. An ESD protection device is in the lid. The ESD protection device is coupled to the electronic circuit.

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

Abstract: A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: A method for manufacturing a display device includes a first step of preparing a first substrate which has a first area to be etched and a second area located at a periphery of the first area and which has a display element on its surface, a second step of etching and removing the first area of the first substrate, a third step of forming a second substrate on a surface of the first substrate that is opposite to the surface on which the display element is located, and a fourth step of removing the second area of the first substrate.