Abstract: Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill of interconnect channels in the IC substrate. The Cu layer, along with reflow agent layer, may then be reflowed into the interconnect channels, forming a Cu alloy with improved gap-fill and electromigration performance. Other embodiments are also described.

Abstract: An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoxOy layer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A semiconductor device includes a semiconductor layer, an electrode pad that is composed of Au and is provided on the semiconductor layer, a silicon nitride film provided on the semiconductor layer and the electrode pad so that an end portion of the silicon nitride film is located, and a metal layer that contacts a part of a surface of the electrode pad and the end portion of the silicon nitride film and is provided so that another part of the surface of the electrode pad is exposed, the metal layer including any of Ti, Ta and Pt.

Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

Abstract: A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

Abstract: A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer.

Abstract: An electronic component is described that includes a metallic layer on a substrate that is made of a semiconductor material and a diffusion barrier layer that is made of a material that has a small diffusion coefficient for the metal of the metallic layer which is formed between the metallic layer and the substrate.

Abstract: A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

Abstract: A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: A sputtering target consists of high purity Nb of which Ta content is 3000 ppm or less and oxygen content is 200 ppm or less. Dispersion of the Ta content in all the sputtering target is within ±30% as a whole target. Dispersion of the oxygen content is within ±80% as a whole target. According to such sputtering target, an interconnection film of low resistivity can be realized. In addition, each grain of Nb in the sputtering target has a grain diameter in the range of 0.1 to 10 times an average grain diameter and ratios of grain sizes of adjacent grains are in the range of 0.1 to 10. According to such sputtering target, giant dust can be largely suppressed from occurring. The sputtering target is suitable for forming a Nb film as liner material of an Al interconnection.

Abstract: The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).

Abstract: Provided is a method for manufacturing a semiconductor device having favorable electric characteristics with a high yield. A groove and/or a contact hole reaching a semiconductor region or a conductive region is formed in an insulating film covering the semiconductor region or the conductive region; a first conductive film is formed in the groove and/or the contact hole; the first conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas and to an atmosphere containing water to be fluidized partially or entirely; and a second conductive film is formed over the first conductive film.

Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.

Abstract: A method and apparatus for authenticating items having a security mark containing a DNA fragment to prevent fraud uses a Raman spectrometer to generate a response spectrum from monochrome incident beam on the security mark on an item. Gross fluorescence is removed from the security mark response spectrum to produce a Raman security mark response spectrum. Peaks in the Raman security mark response spectrum are detected to generate Raman security mark peak data. The Raman security mark peak data is compared to a Raman peak library to determine if there is a match. The item is indicated as being authentic if a match of the Raman security mark peak data is found in the Raman peak library.

Abstract: A printed circuit board includes a substrate having a surface, a circuit layer having a plurality of electrical traces formed on the surface, and an electrically conductive metal layer formed on the circuit layer. The circuit layer is comprised of a composite of carbon nano-tubes and metallic nano-particles.

Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.

Abstract: A method is disclosed that uses solid precursors for semiconductor processing. A solid precursor is provided in a storage container. The solid precursor is transformed into a liquid state in the storage container. The liquid state precursor is transported from the storage container to a liquid holding container. The liquid state precursor is transported from the liquid holding container to a reaction chamber. The molten precursor allows the precursor to be metered in the liquid state. The storage container can be heated only when necessary to replenish the liquid holding container, thereby reducing the possibility of thermal decomposition of the precursor.

Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A metal electrode is used for a pair with a semiconductor so as to sandwich a high-dielectric constant thin film between the metal electrode and the semiconductor. A metal electrode 13 comprises a metal film 11 formed of a first electrode material, and a characteristic control film 10 containing a second electrode material. The characteristic control film 10 is formed between the high-dielectric constant thin film 9 and the metal film 11. C is added to the characteristic control film 10. The addition of C reduces the crystal grain diameter of the material constituting the characteristic control film 10, and suppresses fluctuation of a Vth (threshold voltage).

Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Abstract: This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b).

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: Described is a player activated game system, particularly adapted for playing instant lottery type games, that includes a game device having a computer containing at least one game, an electronic display and a card interface adapted to receive a game card having data that represents a particular game outcome such that connection of the card to the interface can result the game being played by the device with the particular outcome displayed on the display. Also described are lottery tickets or game cards that are adapted use with the game devices along with methods of manufacturing the game cards.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.

Abstract: A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

Abstract: Disclosed is a stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate. The stress buffer structure includes at least one polymer layer formed on the face of the semiconductor substrate and a plurality of metal plates disposed over the polymer layer, wherein the metal plates is physically and electrically isolated from the bond pads of the semiconductor substrate. The disclosed stress buffer structure provides protection to semiconductor components that are sensitive to stress. Also disclosed are semiconductor packages having the disclosed stress buffer structure and the methods of making the semiconductor packages.

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed.

Abstract: A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer.

Abstract: In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Abstract: The invention includes a first step for forming a first conductive layer composed of a high melting point metal to be in contact with an insulating layer; and a second step for forming a second conductive layer by discharging a composition containing a conductive material so as to be in contact with the first conductive layer. The first conductive layer is formed prior to forming the second conductive layer by droplet discharging, and hence, adhesiveness and peel resistance of the second conductive layer are improved. Furthermore, the insulating layer is covered with the first conductive layer, thereby preventing damage or destruction of the insulating layer.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.

Abstract: Disclosed is an electrode for semiconductor devices capable of suppressing the generation of hillocks and reducing the resistivity, which is suitable for an active matrixed liquid crystal display and the like in which a thin film transistor is used; its fabrication method; and a sputtering target for forming the electrode film for semiconductor devices. The electrode for semiconductor devices is made of an Al alloy containing the one or more alloying elements selected from Fe, Co, Ni, Ru, Rh and Ir, in a total amount from 0.1 to 10 At %, or one or more alloying elements selected from rare earth elements, in a total amount from 0.05 to 15 at %.