Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

Abstract: The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap.

Abstract: A semiconductor device includes a semiconductor layer, an electrode pad that is composed of Au and is provided on the semiconductor layer, a silicon nitride film provided on the semiconductor layer and the electrode pad so that an end portion of the silicon nitride film is located, and a metal layer that contacts a part of a surface of the electrode pad and the end portion of the silicon nitride film and is provided so that another part of the surface of the electrode pad is exposed, the metal layer including any of Ti, Ta and Pt.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

Abstract: A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the insulating film. The copper interconnection includes: a first copper interconnection having a relatively narrow width; and a second copper interconnection having a relatively wide width. The first copper interconnection has the top surface thereof principally composed of copper, and the second copper interconnection has the top surface thereof principally composed of copper.

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. The HfSiON film may be formed by atomic layer deposition. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. The titanium nitride and the tantalum may be formed by atomic layer deposition.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the polymer; forming a metal layer to fill the groove which is formed with the insulation layer on the sidewall thereof; and back-grinding a backside of the wafer to expose the metal layer filled in the groove.

Abstract: A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.

Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.

Abstract: To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating films, and the barrier insulating films contain a component of an organic silica containing unsaturated hydrocarbon and amorphous carbon. The copper-containing wirings are covered by the barrier insulating films that contain a component that is in an organic silica structure containing unsaturated hydrocarbon and amorphous carbon. Accordingly, inter-wiring capacitance is reduced without deteriorating reliability of the copper-containing wiring, thereby realizing a high-speed LSI with low power consumption.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between adjacent ones of the plurality of first interconnects in the first interlayer insulating film, and a cap insulating film is formed in a region located over the void and between the interconnects. Respective widths of a lower end and an upper end of the void are substantially the same as a gap between the interconnects located adjacent to the void, and the lower end of the void is located lower than lower ends of the first interconnects located adjacent to the void.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g.

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: Methods for forming passivated stoichiometric metal nitride films are provided along with structures incorporating such films. The preferred methods include contacting a substrate with alternating and sequential pulses of a metal source chemical, one or more plasma-excited species of hydrogen and a nitrogen source chemical to form a stoichiometric metal nitride film, followed by exposure of the stoichiometric metal nitride film to a source chemical of a passivating species to form a passivation layer over the stoichiometric metal nitride film.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer formed on the first interlayer dielectric layer and having a second contact plug, and a third interlayer dielectric layer formed on the second interlayer dielectric layer and having a third contact plug, wherein the first to third contact plugs are connected to each other.

Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.

Abstract: Tungsten nitride films were deposited on heated substrates by the reaction of vapors of tungsten bis(alkylimide)bis(dialkylamide) and a Lewis base or a hydrogen plasma. For example, vapors of tungsten bis(tert-butylimide)bis(dimethylamide) and ammonia gas supplied in alternate doses to surfaces heated to 300° C. produced coatings of tungsten nitride having very uniform thickness and excellent step coverage in holes with aspect ratios up to at least 40:1. The films are metallic and good electrical conductors. Suitable applications in microelectronics include barriers to the diffusion of copper and electrodes for capacitors. Similar processes deposit molybdenum nitride, which is suitable for layers alternating with silicon in X-ray mirrors.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.

Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.

Abstract: A thin-film transistor substrate in which an aluminum alloy film composing a source/drain wiring is directly connected with a transparent electrode. The thin-film transistor substrate includes a gate wiring, and source wiring and drain wiring, the gate wiring and the source and drain wiring being arranged orthogonally to each other. The single-layer aluminum alloy film composing the gate wiring and the single-layer aluminum alloy film composing the source wiring and the drain wiring are the same in composition. Furthermore, display devices can be mounted with the above thin-film transistor substrates.

Abstract: In order to improve the characteristic of the PZT film (insulation film of capacitor) of the PZT capacitor, after forming the amorphous PZT film, the amorphous PZT film is crystallized from at least the upper surface of the amorphous PZT film to form the PZT crystal film by employing the process whose sequence is reverse to that of the conventional process. In this case, the amorphous PZT film, which contains excessive oxygen and formed on the upper surface of the amorphous PZT film, is used as a seed.

Abstract: The application discloses a security mark consisting of a plurality of layers, of which the cover layers are highly conductive films and the layers of the card core are films of varying transparency. One layer carries information, which can be read directly, if desired, above a security print, while the transparent conductive layer has an additional security markings, such as biometric or product identifiers marking which can be read conductively only with the aid of a special reader. All the layers consist of polymers, papers or mixtures which can be fused together to form a laminate which is fused together. The conductive layers form conductive traces which may be formed with single-walled or multi walled nano tubes or they can be formed from multiple layers or dispersions containing, carbon nano tubes, carbon nano tubes/antimony tin oxide, carbon nano tubes/platinum, or carbon nano tubes/silver, carbon, silver or carbon nano tubes/silver-cloride.

Abstract: An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal.

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of absorbing hydrogen with decrease in temperature, and releasing hydrogen with increase in temperature. A conductive tungsten plug is provided on the layer in the opening.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

Abstract: A semiconductor device according to the present invention includes: a lower wire having copper as a main component; an insulating film formed on the lower wire; an upper wire formed on the insulating film; a tungsten plug penetrating through the insulating film and formed of tungsten for electrically connecting the lower wire and the upper wire; and a barrier layer interposed between the lower wire and the tungsten plug; and the barrier layer including a tantalum film contacting the lower wire and a titanium nitride film contacting the tungsten plug.

Abstract: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.

Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.

Abstract: A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Abstract: The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first conductive layer, and a third conductive layer introduced over the second conductive layer. One of the first conductive layer, the second conductive layer, and the third conductive layer comprises titanium-niobium (Ti—Nb).

Abstract: A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon.

Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.

Abstract: A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed between two surfaces of a dielectric material, wherein the first liner layer is in direct contact with at least a portion of a conductive wiring material of an underneath interconnect layer; a noble metal layer disposed on the first liner layer at least in the opening; and a conductive wiring material disposed on the noble metal layer, the conductive wiring material substantially filling the opening; wherein the first liner layer, the noble metal layer and the conductive wiring material are coplanar with the two surfaces of the dielectric material of the intermediate interconnect structure, and the noble metal layer includes a different material than the first liner layer.

Abstract: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.

Abstract: A metallization layer that includes a tantalum layer located on the component, a tantalum silicide layer located on the tantalum layer, and a platinum silicide layer located on the tantalum silicide layer. In another embodiment the invention is a component having a metallization layer on the component. In another embodiment, the metallization layer has a post-annealing adhesive strength to silicon of at least about 100 MPa as measured by a mechanical shear test after exposure to a temperature of about 600° C. for about 30 minutes, and the metallization layer remains structurally intact after exposure to a temperature of about 600° C. for about 1000 hours. The metallization is useful for bonding with brazing alloys.

Abstract: A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

Abstract: An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.