Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.

Abstract: Methods and apparatus for performing physical vapor deposition in a reactor chamber to form aluminum material on a substrate including: depositing a first aluminum layer atop a substrate to form a first aluminum region having a first grain size and a second aluminum layer atop the first aluminum layer, wherein the second aluminum layer has a second grain size larger than the first grain size; and depositing aluminum atop the second aluminum layer under conditions sufficient to increase the second grain size.

Abstract: Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a revised EM length, based upon, at least in part, the edit. Embodiments may also include generating one or more EM length breakpoints based upon, at least in part, the revised EM length and one or more EM rules.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: A display device and a manufacturing method of the same are provided. The display device includes a frame, a pressure sensor, and a pressure sensing module. When a touch portion receives external pressure, a resistance value of the resistor changes, and a corresponding pressure sensing signal is output. The pressure sensing module outputs an execution signal according to the pressure sensing signal to realize a pressure touch function on a side of the frame. This eliminates a need to make holes in a side of the frame, which eliminates a mechanical button and improves dustproof and waterproof performance of the display device.

Abstract: An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.

Abstract: A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wtppm or less of Mn are disclosed. The first and/or the second alloy sputtering target can further comprise one or more elements selected from among Sb, Zr, Ti, Cr, Ag, Au, Cd, In and As in a total amount of 1.0 wtppm or less. A semiconductor element wiring formed by the use of the above targets is also disclosed. The above copper alloy sputtering target allows the formation of a wiring material for a semiconductor element, in particular, a seed layer being stable, uniform and free from the occurrence of coagulation during electrolytic copper plating and exhibits excellent sputtering film formation characteristics.

Abstract: A semiconductor structure includes a first dielectric layer disposed over a substrate; a first metal feature and a second metal feature embedded in the first dielectric layer and spaced from each other; an etch stop layer disposed between the first and second metal features and on sidewalls of the first dielectric layer; a second dielectric layer disposed over the etch stop layer and between the first and second metal features; and an air gap surrounded by the second dielectric layer and disposed between the first and second metal features.

Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.

Abstract: Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.

Abstract: A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.

Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

Abstract: A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a trench; mounting an integrated circuit device on the leadframe; forming a top encapsulation on the leadframe and the trench; forming a lead having a lead protrusion and a peripheral groove, the lead protrusion and the peripheral groove formed from etching the trench at a leadframe bottom side; and forming a bottom encapsulation surrounding a lead bottom side of the lead.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.

Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.

Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.