Abstract: Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

Abstract: A photochemical electrode includes: an electrically conductive layer; and a photoexcitation material layer provided over the electrically conductive layer and including a photoexcitation material, wherein the photoexcitation material layer is one of a first photoexcitation material layer in which a potential of the conduction band minimum decreases from a second surface opposite to a first surface on the side of the electrically conductive layer toward the first surface and a second photoexcitation material layer in which a potential of the valence band maximum decreases from the second surface toward the first surface.

Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).

Abstract: An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is Al(1?x)InxN, where 0?x?1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

Abstract: A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers.

Abstract: A layer of a crystal of a nitride of a group 13 element selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof includes an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, and the high-luminance light-emitting part has a portion extending along an m-plane of the crystal of the nitride of the group 13 element, when the upper surface is observed by cathode luminescence. The upper surface has an arithmetic average roughness Ra of 0.05 nm or more and 1.0 nm or less.

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

Abstract: The present invention provides a nitride semiconductor device capable of forming a half-bridge circuit and suppressing changes in current collapse characteristics. A first transistor of the present invention includes a first nitride semiconductor layer, and a first gate electrode, a first source electrode and a first drain electrode formed thereon. The second transistor includes a second nitride semiconductor layer, and a second gate electrode, a second source electrode and a second drain electrode formed thereon. The source electrode is electrically connected to a lower region of a first region on the substrate, the second source electrode is electrically connected to a lower region of a second region on the substrate, and a first insulating region is disposed between a portion corresponding to the first region on the substrate and a portion corresponding to the second region on the substrate.

Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.

Abstract: A semiconductor device of an embodiment includes: a nitride semiconductor layer including a first GaN region of n-type, a second GaN region of n-type on the first GaN region, a third GaN region of p-type on the first GaN region, a fourth GaN region of p-type sandwiching the second GaN region with the third GaN region, a fifth GaN region of p-type on the third GaN region, a sixth GaN region of p-type sandwiching the second GaN region with the fifth GaN region, a seventh GaN region of n-type on the fifth GaN region, an eighth GaN region of n-type on the sixth GaN region, a trench between the seventh GaN region and the eighth GaN region, the trench having an inclination angle of less than 90 degrees; a gate insulating layer including an aluminum nitride film in the trench; a gate electrode; a first electrode; and a second electrode.

Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

Abstract: An LED pixel device is disclosed. The LED pixel device includes a first light-transmitting substrate, a second light-transmitting substrate overlying the first light-transmitting substrate, a third light-transmitting substrate overlying the second light-transmitting substrate, a first light-emitting cell underlying the first light-transmitting substrate, a second light-emitting cell interposed between the first light-transmitting substrate and the second light-transmitting substrate, and a third light-emitting cell interposed between the second light-transmitting substrate and the third light-transmitting substrate. The first light-emitting cell, the second light-emitting cell, and the third light-emitting cell emit light of different wavelengths.

Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.

Abstract: A light emitting device includes a light emitting element having an upper emission face, a lower face and a lateral face(s); a reflecting member having an upper face, a lower face and inner and outer lateral faces, wherein the inner lateral face(s) is disposed on the lateral face side of the light emitting element; a wavelength conversion member having an upper emission face, a lower face and a lateral face(s), wherein the lower face is disposed on the upper emission face of the light emitting element and on the upper face of reflecting member; and a cover member having inner and outer lateral faces, wherein the inner lateral face(s) completely covers the lateral face(s) of the wavelength conversion member. The cover member contains a reflecting substance and a coloring substance, and the body color of the wavelength conversion member and body color of the cover member are the same or similar in color.

Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

Abstract: A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.

Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.

Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: A method of manufacture and structure for an acoustic resonator device having a hybrid piezoelectric stack with a strained single crystal layer and a thermally-treated polycrystalline layer. The method can include forming a strained single crystal piezoelectric layer overlying the nucleation layer and having a strain condition and piezoelectric layer parameters, wherein the strain condition is modulated by nucleation growth parameters and piezoelectric layer parameters to improve one or more piezoelectric properties of the strained single crystal piezoelectric layer. Further, the method can include forming a polycrystalline piezoelectric layer overlying the strained single crystal piezoelectric layer, and performing a thermal treatment on the polycrystalline piezoelectric layer to form a recrystallized polycrystalline piezoelectric layer. The resulting device with this hybrid piezoelectric stack exhibits improved electromechanical coupling and wide bandwidth performance.

Abstract: The present disclosure provides a protection circuit for protecting a light emitting element, a pixel unit including the protection circuit, a display panel, and a driving method of the protection circuit. The protection circuit for protecting the light emitting element includes: a bonding protection sub-circuit including a sacrificial metal region, configured to electrically couple the sacrificial metal region to an anode pad and a cathode pad on the backplane for bonding the light emitting element during a period of bonding the light emitting element to the backplane.

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: A semiconductor device of an embodiment includes a SiC layer including a first trench, a second trench having first and second regions, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region, a p-type fourth SiC region between the first trench and the first SiC region, and a p-type fifth SiC region between the second trench and the first SiC region and having a first portion and a second portion, a gate electrode in the first trench, a first electrode in the second trench, and a second electrode. A distance between the first trench and the first region is greater than a distance between the first trench and the second region, the first portion is separated from the fourth SiC region, the second portion contacts the fourth SiC region, the first region contacts the first portion, and the second region contacts the second portion.

Abstract: The present invention relates to an epitaxial structure of Ga-face group III nitride, its active device, and its gate protection device. The epitaxial structure of Ga-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlyGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.

Abstract: Apparatus and circuits including transistors with different gate stack materials and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a channel layer formed over the substrate; a first transistor formed over the channel layer, wherein the first transistor comprises a first source region, a first drain region, a first gate structure, and a first polarization modulation portion under the first gate structure; and a second transistor formed over the channel layer, wherein the second transistor comprises a second source region, a second drain region, a second gate structure, and a second polarization modulation portion under the second gate structure, wherein the first polarization modulation portion is made of a material different from that of the second polarization modulation portion.

Abstract: A light emitting device, according to the present embodiment, has a light emitting panel, a flexible wiring substrate, a mold resin and a protective tape. The light emitting panel has a first substrate, which is transparent to light, a plurality of conductor patterns, which are formed on a surface of the first substrate, a plurality of light emitting elements, which are connected to any of the conductor patterns, and a resin layer, which holds the light emitting elements on the first substrate. The flexible wiring substrate has a circuit pattern that is electrically connected with an exposed part of the conductor patterns. The mold resin covers the exposed part of the conductor patterns and an exposed part of the circuit pattern. The protective tape covers the mold resin, and is wound around a joint part of the light emitting panel and the flexible wiring substrate.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

Abstract: An optical coupling structure is disposed on a light output surface of a semiconductor LED to facilitate coupling of light emitted by the semiconductor LED through the light output surface. The optical coupling structures comprise light scattering particles and/or air voids embedded in or coated with a thin layer of a material that has an index of refraction close to or matching the index of refraction of the material forming the light output surface of the semiconductor LED.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.

Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.

Abstract: A multi-wavelength light-emitting diode epitaxial structure comprises of a substrate and at least three light-emitting elements, wherein the light-emitting elements are sequentially stacked on the substrate. For each two adjacent light-emitting elements, the light-emitting element disposed closer to the light-exiting surface has a higher bandgap than that of the light-emitting element disposed farther from the light-exiting surface. Each of the light-emitting elements comprises of an active layer and two cladding layers disposed on two opposite sides of the active layer, and each active layer includes a multiple quantum well structure. Cladding layers of different refractive indexes are arranged incrementally from the substrate to the light-exiting surface. Any given two adjacent cladding layers from two light-emitting elements have a combined thickness of 1 ?m or less. The emission wavelengths of the light-emitting elements are ultraviolet or infrared bands.

Abstract: A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

Abstract: A semiconductor structure includes a substrate having a first region and a second region, an epitaxial layer above the substrate, a first device on the first region, a second device on the second region and an isolation structure on the substrate. The first device includes a first gate electrode, a first source electrode and a first drain electrode disposed at two opposite sides of the first gate electrode. A dielectric layer disposed on the epitaxial layer covers the first gate electrode. The second device includes a second gate electrode disposed on the dielectric layer, second source and drain electrodes disposed at two opposite sides of the second gate electrode. The second source electrode is electrically connected to the first drain electrode. Also, the portions of the epitaxial layer respectively disposed in the first and second regions are isolated from each other by the isolation structure.

Abstract: A semiconductor device is provided, including a substrate, a gate electrode, a first dielectric layer, a source field plate, a second dielectric layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The first dielectric layer is disposed on the gate electrode and has a first recess and a second recess. The source field plate is disposed on the first dielectric layer and extends into the first recess and the second recess. The second dielectric layer is disposed on the source field plate. The source electrode is disposed on the second dielectric layer and electrically connected to the source field plate. The drain electrode is disposed on the second dielectric layer. The first recess and the second recess are located between the gate electrode and the drain electrode.

Abstract: A method of manufacturing a semiconductor device includes: providing a first member comprising: a first substrate, a semiconductor layer disposed on the first substrate and defining a first recess, and a first metal layer disposed above at least a portion other than the first recess, the first member defining a second recess in a region of a surface of the first member including a region directly above the first recess; providing a second member comprising: a second substrate, a second metal layer on or above the second substrate, a third metal layer on the second metal layer, and a fourth metal layer on the third metal layer; and bonding the first member and the second member together by heating the first metal layer and the fourth metal layer while facing each other. The third metal layer impedes interdiffusion between the second metal layer and the fourth metal layer.

Abstract: A light-emitting device is provided, which includes a first semiconductor structure, an active structure, a second semiconductor structure, and a first blocking layer. The first semiconductor structure has a first conductivity type. The active structure is on the first semiconductor structure and has a first dopant. The second semiconductor structure is on the active structure and has a second conductivity type different from the first conductivity type. The first blocking layer is between the second semiconductor structure and the active structure. The first blocking layer has the first dopant with a first doping concentration decreasing along a depth direction from the second semiconductor structure to the first semiconductor structure.

Abstract: A process of forming a nitride semiconductor device is disclosed. The process includes steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region within the recess and simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film and the second SiN film by removing the SiO2 film.

Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

Abstract: A power device includes a substrate including a drift layer and having a first region and a second region, the drift layer having impurities of a first type; a switch formed in the first region; a diode formed in the second region; a metal structure formed over a surface of the substrate, the metal structure having a first thickness over the first region of the substrate and a second thickness over the second region of the substrate, the first thickness and second thickness having at least 3 um in thickness difference; and a zone provided in the drift layer in the second region of the substrate, the zone having impurities of a second type that is different from the first type.

Abstract: The invention relates to an AlInGaN alloy based superluminescent diode, comprising a gallium nitride bulk substrate, a lower cladding layer with n-type electrical conductivity. Further it includes a lower light-guiding layer with n-type electrical conductivity, a light emitting layer, an electron blocking layer with p-type electrical conductivity, an upper light-guiding layer, an upper cladding layer with p-type electrical conductivity, and a subcontact layer with p-type electrical conductivity. The gallium nitride bulk substrate has a spatially varying surface misorientation in the relation to the crystallographic plane M in range of 0° to 10°.

Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.

Abstract: A method of depositing a coating layer comprising gallium nitride on a substrate comprising the steps of: (a) providing the substrate having a plurality of side walls and valleys; (b) forming a first layer of gallium nitride deposited on the substrate, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 400 to 500° C., such that the first layer is formed on the side walls and the valleys; and (c) forming a second layer of gallium nitride deposited on top of the first layer, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 1000 to 1200° C., to obtain the coating layer comprising the first layer of gallium nitride and the second layer of gallium nitride at a thickness ranging from 3.0 to 4.5 ?m.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.

Abstract: A light emitting chip includes a first-type semiconductor layer, a light emitting layer, and a second-type semiconductor layer which are disposed in such order, a passivation layer, and a current spreading layer. The second-type semiconductor layer and the light emitting layer cooperate to form a mesa structure which partially exposes the first-type semiconductor layer. The mesa structure has a lateral surface over which the passivation layer is disposed. The current spreading layer is disposed in contact with the second-type semiconductor layer. A distance between peripheries of a contact surface of the current spreading layer and a top surface of the second-type semiconductor layer is not greater than 5 ?m. A method for producing the chip is also disclosed.

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.