Abstract: Devices, systems and techniques are described for producing and implementing articles and materials having nanoscale and microscale structures that exhibit superhydrophobic, superoleophobic or omniphobic surface properties and other enhanced properties. In one aspect, a surface nanostructure can be formed by adding a silicon-containing buffer layer such as silicon, silicon oxide or silicon nitride layer, followed by metal film deposition and heating to convert the metal film into balled-up, discrete islands to form an etch mask. The buffer layer can be etched using the etch mask to create an array of pillar structures underneath the etch mask, in which the pillar structures have a shape that includes cylinders, negatively tapered rods, or cones and are vertically aligned. In another aspect, a method of fabricating microscale or nanoscale polymer or metal structures on a substrate is made by photolithography and/or nano imprinting lithography.

Abstract: A crystal of a group 13 nitride has an upper surface and lower surface and is composed of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. When the upper surface of the layer of the crystal of the group 13 nitride is observed by cathode luminescence, the upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. A half value width of reflection at the (0002) plane of a X-ray rocking curve on the upper surface is 3000 seconds or less and 20 seconds or more.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first crystal member. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first electrode and the second electrode. The semiconductor member includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The semiconductor member includes a first region, and first and second partial regions. The first region is between the first and second electrodes in the first direction. A second direction from the first region toward the third electrode crosses the first direction. The first crystal member is provided between the first and third electrodes in the second direction.

Abstract: A light-emitting device includes: a light-emitting element; a first light-diffusion layer disposed laterally to the light-emitting element and constituting a first portion of lateral surfaces of the light-emitting device; a second light-diffusion layer disposed above the light-emitting element and the first light-diffusion layer and constituting a second portion of the lateral surfaces of the light-emitting device; a light-control portion disposed between the first light-diffusion layer and the second light-diffusion layer and configured to reflect a portion of light emitted from the light-emitting element; and a first light-reflection layer disposed on the second light-diffusion layer.

Abstract: According to one configuration, an inductor device comprises: core material and one or more electrically conductive paths. The core material is magnetically permeable and surrounds (envelops) the one or more electrically conductive paths. Each of the electrically conductive paths extends through the core material of the inductor device from a first end of the inductor device to a second end of the inductor device. The magnetically permeable core material is operative to confine (guide, carry, convey, localize, etc.) respective magnetic flux generated from current flowing through a respective electrically conductive path. The core material stores the magnetic flux energy (i.e., first magnetic flux) generated from the current flowing through the first electrically conductive path.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A light emitting diode (LED) device includes a light emitting epitaxial layer having opposite first and second surfaces and a plurality of microlenses formed on the first surface. The light emitting epitaxial layer includes a first type semiconductor layer defining the first surface, a second type semiconductor layer defining the second surface, and a light emitting layer disposed between the first and second type semiconductor layers and spaced apart from the first and second surfaces. The microlenses are formed on the first surface and formed of a light transmissible substrate for epitaxial growth of the light emitting epitaxial layer. A method for manufacturing the light emitting diode device is also disclosed.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.

Abstract: A semiconductor device includes a back barrier layer formed over a substrate, a first electron transit layer formed over the back barrier layer, an opening formed in the first electron transit layer and the back barrier layer, a second electron transit layer formed over the first electron transit layer, a side surface of the first electron transit layer at a side surface within the opening, a side surface of the back barrier layer at a side surface within the opening, and a surface of the back barrier layer at a bottom surface within the opening, an electron supply layer formed over the second electron transit layer, a drain electrode formed over the electron supply layer within the opening, and a gate electrode formed to cover a side surface of the electron supply layer at a side surface within the opening from an edge part of the opening.

Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: The present invention proposes a set of impurity doping configurations for GaN buffer in an AlGaN/GaN HEMT device to improve breakdown characteristics of the device. The breakdown characteristics depend on a unique mix of donor and acceptor traps and using carbon as a dopant increases both donor and acceptor trap concentrations, resulting in a trade-off in breakdown voltage improvement and device performance. A modified silicon and carbon co-doping is proposed, which enables independent control over donor and acceptor trap concentrations in the buffer, thus potentially improving breakdown characteristics of the device without adversely affecting the device performance.

Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of the crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride.

Abstract: A mobile device including: at least an imaging element; and a light-emitting device that irradiates a subject in accordance with imaging of the imaging element, in which the light-emitting device includes a semiconductor light-emitting element, and the difference of the normalized spectral power distribution at a wavelength of 580 nm and a value B representing a difference between normalized spectral power distributions in a wavelength range from 540 nm to 610 nm and a wavelength range from 610 nm to 680 nm are appropriate values. By providing a wavelength control element, it is possible to improve the color reproducibility and the like of a captured image. The mobile device achieves both sensitivity improvement and color reproducibility in a trade-off relationship.

Abstract: A semiconductor chip and a method for producing a semiconductor chip are disclosed. In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface, which is formed by a planar region having a plurality of three-dimensional surface structures on the planar region, a nucleation layer composed of oxygen-containing AlN directly disposed on the growth surface and a nitride-based semiconductor layer sequence disposed on the nucleation layer, wherein the semiconductor layer sequence is selectively grown from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.

Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.

Abstract: A display panel and a method for manufacturing the display panel are provided. The method includes providing a first substrate, forming a buffer layer including at least one first buffer layer on a first side of the first substrate; forming a LED structure including a first LED structure on a side of the buffer layer facing away from the first substrate, forming a planarization layer covering the LED structure on a side of the LED structure facing away from the buffer layer, forming an electrode structure connected to the LED units on a side of the planarization layer facing away from the LED structure, and forming a control circuit on a side of the electrode structure facing away from the LED structure, where the control circuit is electrically connected to the electrode structure and configured to control operation states of the LED units.

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.

Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

Abstract: A semiconductor device includes a semiconductor layer, a gate electrode disposed on the semiconductor layer, a first dielectric layer disposed on the semiconductor layer and the gate electrode, a source field plate disposed on the semiconductor layer and the first dielectric layer, a second dielectric layer disposed on the source field plate, and a source electrode disposed on the second dielectric layer and electrically connected to the source field plate. The gate electrode has a first sidewall and a second sidewall respectively disposed on the first side and the second side. The source field plate extends from the first side to the second side. A portion of the source field plate is disposed to correspond to the second sidewall. The semiconductor device further includes a third dielectric layer disposed on the source electrode and a drain structure disposed on the second side.

Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Abstract: An apparatus including a red LED and monolithic multicolor LED pixel and a method of fabricating an LED device is disclosed. The method includes providing a substrate for the wafer. The method also includes forming a light emitting diode (LED) using Hydrazine to dispose above the substrate an Indium Gallium Nitride (InGaN) layer of the LED.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.

Abstract: There is provided a reverse-blocking semiconductor device that has a simple configuration, that is capable of improving a yield in a manufacturing process, and that secures a reverse withstand voltage by using a Schottky junction, and there is provided a method for manufacturing the reverse-blocking semiconductor device.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.

Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.

Abstract: A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.

Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a preparation step S10 for preparing a group III nitride semiconductor substrate having a sapphire substrate having a semipolar plane as a main surface, and a group III nitride semiconductor layer positioned over the main surface, in which a <0002> direction of the sapphire substrate and a <10-10> direction of the group III nitride semiconductor layer do not intersect at right angles in a plan view in a direction perpendicular to the main surface, and a growth step S20 for epitaxially growing a group III nitride semiconductor over the group III nitride semiconductor layer.

Abstract: Methods and structures for forming epitaxial layers of Ill-nitride materials on patterned foreign substrates with low stacking fault densities are described. Semipolar and nonpolar orientations of GaN that are essentially free from stacking faults may be grown from crystal-growth facets of a patterned substrate. Etching can be used to remove stacking faults if present. Crystal growth with an impurity can eliminate crystal growth from a facet that is responsible for stacking fault formation and permit substantially stacking-fault-free growth of the Ill-nitride material.

Abstract: A photoconductive antenna has an array of antenna electrodes on or in a photoconductive substrate. The photoconductive substrate is irradiated with light from a pulsed laser via micro-lenses above respective gaps between antenna electrodes. This makes the photoconductive substrate temporarily conductive, causing pulsed electric antenna currents that can be used for transmission of electromagnetic radiation in the Terahertz range. The bias circuit of the antenna is configured to determine voltages applied to the antenna electrodes by capacitive voltage division over a series of successive capacitors, each capacitor being formed by the antenna electrodes of a respective pair of successive ones of the antenna electrodes in the array as plates of the capacitor adjacent to a respective one of the gaps.

Abstract: A light-emitting element according to an embodiment comprises: a light-emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer formed between the first and second conductive type semiconductor layers; a reflective layer formed on the second conductive type semiconductor layer; a capping layer formed on the reflective layer to surround the reflective layer; a first electrode electrically connected with the first conductive type semiconductor layer; a first bonding pad electrically connected with the first electrode; and a second bonding pad electrically connected with the second electrode, wherein the light-emitting structure includes a recess extending to a region of the first conductive type semiconductor layer through the second conductive type semiconductor layer and the active layer; the first electrode is formed within the recess and electrically connected with the first conductive type semiconductor layer, and includes a

Abstract: An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further includes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies.

Abstract: A light emitting device includes a wavelength conversion element, and an excitation light source which radiates excitation light to the wavelength conversion element. The wavelength conversion element includes a support member having a supporting surface, and a wavelength conversion member disposed on the supporting surface so as to be contained within the support member when the support member is viewed from the supporting surface side. An outer peripheral region on the support member, which is an outer peripheral portion of an arrangement region including the wavelength conversion member and is exposed from the wavelength conversion member, includes a light absorbing portion which can absorb first light having same wavelength as the excitation light or a light scattering portion which can scatter the first light. The arrangement region includes a reflective member which is disposed between the wavelength conversion member and the support member, and is different from the support member.

Abstract: A semiconductor device substrate including: a substrate; a buffer layer which is provided on the substrate and made of a nitride semiconductor; and a device active layer which is formed of a nitride semiconductor layer provided on the buffer layer, the semiconductor device substrate in that the buffer layer includes: a first region which contains carbon and iron; a second region which is provided on the first region and has average concentration of iron lower than that in the first region and average concentration of carbon higher than that in the first region, and the average concentration of the carbon in the second region is lower than the average concentration of the iron in the first region. The semiconductor device substrate which can suppress a transverse leak current in a high-temperature operation of a device while suppressing a longitudinal leak current and can inhibit a current collapse phenomenon is provided.

Abstract: Some embodiments of the disclosure provide for a lighting system including a substrate. The lighting system includes several blue light emitting diodes (LEDs) supported by the substrate. The lighting system includes at least one red LED supported by the substrate. The lighting system includes a light conversion material covering the blue LEDs and the at least one red LED.

Abstract: According to one embodiment, a substrate processing apparatus comprises a chamber for a substrate that has a target film thereon. The apparatus includes a first gas introducing unit to introduce a precursor gas into the chamber, a second gas introducing unit that introduces a etching gas for etching the target film into the chamber, and a controller configured to control the first gas introducing unit and the second gas introducing unit to cause the first gas and the second gas to be alternately introduced to the chamber.

Abstract: A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an ‘ON’ state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.

Abstract: A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.

Abstract: An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.

Abstract: A hydrosilylation curable polysiloxane comprising at least one of units of formula (I) and units of formula (II), wherein Ar is C6-C20 aryl, R1 is C2-C20 alkenyl, and R2, R3, R4 and R5 independently are C1-C20 hydrocarbyl.

Abstract: Implementations of an ohmic contact for a gallium nitride (GaN) device may include: a first layer including aluminum coupled directly with the GaN device; the GaN having a heterostructure with an undoped GaN channel and a semi-insulating aluminum gallium nitride (AlGaN) barrier, all the foregoing operatively coupled with a substrate; a second layer including titanium coupled over the first layer; and a third layer including an anti-diffusion material coupled with the second layer. A passivation layer may be coupled between the AlGaN barrier and the first layer of the ohmic contact. The passivation layer may surround the ohmic contact.

Abstract: A semiconductor structure, a high electron mobility transistor (HEMT), and a method for fabricating a semiconductor structure are provided. The semiconductor structure includes a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a GaN-based semiconductor layer. The substrate has a pit exposed from a top surface of the substrate. The flowable dielectric material pad layer is formed in the pit, and a top surface of the flowable dielectric material pad layer is below the top surface of the substrate. The reflow protection layer is formed on the substrate and the top surface of the flowable dielectric material pad layer. The GaN-based semiconductor layer is disposed over the substrate.

Abstract: A display device and a method of manufacturing the same are provided. A display device includes: a substrate, a semiconductor layer on the substrate, a gate insulating pattern on the semiconductor layer, a plurality of gate electrodes on the gate insulating pattern, and a thin-film transistor spaced apart from the gate insulating pattern, the thin-film transistor including: a source electrode contacting the top surface of the semiconductor layer, a source-drain electrode adjacent to the source electrode, a first of the plurality of gate electrodes being between the source-drain electrode and the source electrode, and a drain electrode adjacent to the source-drain electrode, a second of the plurality of gate electrodes being between the drain electrode and the source-drain electrode.

Abstract: A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.