Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer.

Abstract: A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base. A depletion mode gallium nitride field-effect transistor (GaN FET) and an enhancement mode laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS FET) are also coupled with the base. The gate connector and a gate contact of the LDMOS FET are both included in a first electrical node, the source connector and a source contact of the LDMOS FET are both included in a second electrical node, and the drain connector and a drain contact of the GaN FET are both included in a third electrical node. The GaN FET and LDMOS FET together form a cascode that operates as an enhancement mode amplifier. The semiconductor package does not include an interposer between the GaN FET and the base or between the LDMOS FET and the base.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A semiconductor structure includes a substrate, a first graded transition body over the substrate, a second transition body and a III-Nitride semiconductor layer over the second transition body. The first graded transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The second transition body has a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body. The second transition body includes at least two transition modules each having at least three interlayers. The first graded transition body and the second transition body reducing strain for the semiconductor structure.

Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.

Abstract: Light-emitting devices and methods, wherein, in some embodiments, the devices each include a first mirror having a first face, wherein the first mirror includes a metal and, in some embodiments, is a grown-epitaxial metal mirror (GEMM); and an epitaxial structure, wherein the epitaxial structure is lattice matched with and in contact with at least a first portion of the first face of the first mirror, wherein the epitaxial structure includes an active region configured to emit light at a wavelength ?, and wherein the active region is located a first non-zero distance away from the first face of the first mirror such that there is plasmonic coupling between the active region and the first mirror.

Abstract: A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part.

Abstract: The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film is formed above a gate electrode above a substrate with an interlayer insulation film interposed and a source electrode coupled to a barrier layer on one side of the gate electrode and a drain electrode coupled to the barrier layer on the other side of the gate electrode are formed by etching the electrically-conductive film. On this occasion, the source electrode is etched so as to have a shape extending beyond above the gate electrode to the side of the drain electrode and having a gap (opening) above the gate electrode. Successively, hydrogen annealing is applied to the substrate. In this way, by forming the gap at a source field plate section of the source electrode, it is possible to efficiently supply hydrogen in the region where a channel is formed in the hydrogen annealing process.

Abstract: A self-supporting substrate includes a first nitride layer grown by a hydride vapor deposition method or ammonothermal method and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium; and a second nitride layer grown by a sodium flux method on the first nitride layer and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium. The first nitride layer includes a plurality of single crystal grains arranged therein and extending between a pair of main faces of the first nitride layer. The second nitride layer includes a plurality of single crystal grains arranged therein and extending between a pair of main faces of the second nitride layer. The first nitride layer has a thickness larger than a thickness of the second nitride layer.

Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used.

Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first electrode on the second nitride semiconductor layer, a second electrode on the second nitride semiconductor layer, a gate electrode located between the first electrode and the second electrode, and a first insulating layer located at least between the gate electrode and the second electrode on the second nitride semiconductor layer, the first insulating layer being an oxide of at least one first element selected from the group consisting of Hf, Zr, and Ti, and containing 5×1019 cm?3 or more of at least one second element selected from the group consisting of F, H, D, V, Nb, and Ta, and 5×1019 cm?3 or more of at least one third element selected from the group consisting of N, P, As, Sb, Bi, Be, Mg, Ca, Sr, Ba, Sc, Y, and lanthanoids.

Abstract: A gallium nitride thin film can be formed on a substrate at a low temperature (e.g., not higher than 600° C.) by applying a laser to resonantly excite molecules of a first precursor that contains nitrogen, in which the laser has a wavelength that is selected to match a vibration mode and/or a vibrational-rotational mode of the molecules of the first precursor. A second precursor is provided in which the excited first precursor and the second precursor react to form a nitride that is deposited on the substrate. For example, the second precursor may include gallium, and the nitride may be gallium nitride. Other nitride films can be produced in a similar manner.

Abstract: A compound semiconductor film structure includes a substrate, a first compound semiconductor epitaxial layer and a second compound semiconductor epitaxial layer. The substrate has a top surface. The first compound semiconductor epitaxial layer is formed on the top surface and has an epitaxial interface and at least one recess, wherein the epitaxial interface is disposed on one side of the first compound semiconductor epitaxial layer opposite to the side of the first compound semiconductor epitaxial layer facing the top surface, and the at least one recess is formed in the first compound semiconductor epitaxial layer. The second compound semiconductor epitaxial layer formed on the epitaxial interface. The top surface and the bottom of recess are separated by a distance substantially ranging between 0.8 ?m and 1.3 ?m.

Abstract: Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Abstract: The present techniques provide a method for producing a Group III nitride semiconductor light-emitting device, which method is intended to grow semiconductor layers with high crystallinity on a sapphire substrate having a small area ratio of a base surface to a main surface. In preparing a substrate, a substrate is prepared, of which a main surface has a c-plane base surface and a plurality of projections protruding from the base surface, and the area ratio of the base surface to the main surface is 8% to 32%. In preparing an AlN buffer layer, the AlN buffer layer having a thickness of 34 nm to 14 nm is formed through MOCVD. The thickness of the AlN buffer layer is decreased as the area ratio of the base surface to the main surface of the substrate is increased.

Abstract: Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting boron nitride or amorphous carbon into an undercooled state followed by quenching. Exemplary new materials disclosed herein can be ferromagnetic and/or harder than diamond. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. A novel phase of solid carbon has structure different than diamond and graphite.

Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked. A connection electrode is positioned above the light-emitting structure. The connection electrode includes a connection metal layer electrically connected to at least one of the first and second semiconductor layers. A UBM pattern is on the connection electrode. A connection terminal is on the UBM pattern. The connection metal layer includes a first metal element. A heat conductivity of the first metal element is higher than that of gold (Au). The connection terminal includes a second metal element. A first reactivity of the first metal element with the second metal element is lower than a second reactivity of gold (Au) with the second metal element.

Abstract: A compound semiconductor device disclosed herein includes: a GaN carrier transit layer formed on a substrate; a barrier layer formed on the carrier transit layer; a first recess and a second recess formed in the barrier layer; a first InAlN layer and a second InAlN layer formed in the first recess and the second recess respectively, a composition ratio of In in the InAlN layers being equal to or more than 17% and equal to or less than 18%; a source electrode formed on the first InAlN layer; a drain electrode formed on the second InAlN layer; and a gate electrode formed on the barrier layer.

Abstract: A seed crystal layer is provided on a supporting body. A laser light is irradiated from a side of the supporting body to provide an altered portion along an interface between the supporting body and seed crystal layer. The altered layer is composed of a nitride of a group 13 element and has a portion into which dislocation defects are introduced or an amorphous portion.

Abstract: According to one embodiment, a semiconductor substrate includes a first semiconductor layer including Alx1Ga1-x1N (0<x1?1) and including carbon and oxygen, and a second semiconductor layer including Alx2Ga1-x2N (0<x2<x1) and including carbon and oxygen. A second ratio of a carbon concentration of the second semiconductor layer to an oxygen concentration of the second semiconductor layer is 730 or more.

Abstract: An InGaAlP Schottky field effect transistor with stepped bandgap ohmic contact, comprising: a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer, an intermediate bandgap layer, a cap layer and an ohmic metal layer sequentially formed on a compound semiconductor substrate; wherein the Schottky barrier layer is made of InGaAlP; the ohmic metal layer and the cap layer form an ohmic contact. The Schottky barrier layer, the intermediate bandgap layer and the cap layer have a Schottky-barrier-layer bandgap, an intermediate bandgap and a cap-layer bandgap respectively, wherein the intermediate bandgap is less than the Schottky-barrier-layer bandgap and greater than the cap-layer bandgap.

Abstract: A semiconductor light-emitting element including a first semiconductor layer of a first conductivity type; a light-emitting functional layer that includes first and second light-emitting layers; and a second semiconductor layer of a conductivity type opposite to the conductivity type of the first semiconductor layer. The first light-emitting layer has a first base layer with a composition subject to stress strain from the first semiconductor layer; a first quantum well layer that retains a segment shape of the first base segment; and a first barrier layer that has a flat surface flattened by embedding the first base layer and the first quantum well layer. The second light-emitting layer has a second base layer that has a composition subject to stress strain from the first barrier layer; a second quantum well layer that retains a segment shape of the second base segment; and a second barrier layer.

Abstract: A composite semiconductor substrate being able to improve voltage withstanding and crystalline quality is provided. A composite semiconductor substrate is equipped with an Si (silicon) substrate, an SiC (silicon carbide) layer formed on the surface of the Si substrate, an AlN (aluminum nitride) layer formed on the surface of the SiC layer, a composite layer formed on the surface of the AlN layer, and a GaN (gallium nitride) layer formed on the surface of the composite layer. The composite layer includes an AlN (aluminum nitride) layer and a GaN layer formed on the surface of the AlN layer. In at least one composite layer, the average density of C and Fe in the GaN layer is higher than the average density of C and Fe in the AlN layer.

Abstract: A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm?2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.

Abstract: In one instance, the invention provides a bulk crystal of group III nitride having a thickness of more than 1 mm without cracking above the sides of a seed crystal. This bulk group III nitride crystal is expressed as Gax1Aly1In1-x1-y1N (0?x1?1, 0?x1+y1?1) and the seed crystal is expressed as Gax2Aly2In1-x2-y2N (0?x2?1, 0?x2+y2?1). The bulk crystal of group III nitride can be grown in supercritical ammonia or a melt of group III metal using at least one seed crystal having basal planes of c-orientation and sidewalls of m-orientation. By exposing only c-planes and m-planes in this instance, cracks originating from the sides of the seed crystal are avoided.

Abstract: A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. A first portion of the first crystalline semiconductor material in first semiconductor strip is converted to a dielectric material, where a second portion of the first crystalline semiconductor material remains unconverted. Gate structures are formed over the first semiconductor strip and source/drain regions are formed on opposing sides of the gate structures.

Abstract: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction, wherein the multi-quantum-well structure has at least one emission region and multiple transport regions which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission regions, and wherein the quantum-well layers in the transport regions and in the emission regions are oriented perpendicularly to the growth direction with exception of a junction region between adjacent transport regions and emission regions.

Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.

Abstract: A semiconductor light emitting device package is provided and includes a light emitting diode (LED) chip including a first electrode and a second electrode, the LED chip having a first surface on which the first electrode and the second electrode are disposed, and a second surface opposing the first surface; a dam structure disposed on the first surface, an outside edge of the dam structure being co-planar with an outside edge of the LED chip; and a wavelength conversion layer disposed on side surfaces of the LED chip, the second surface of the LED chip, and a surface of the dam structure, the wavelength conversion layer containing a wavelength conversion material.

Abstract: When a nitride semiconductor layer into which impurity ions have been implanted is subjected to annealing after a protective film is provided on the nitride semiconductor layer, vacancy defects may be disadvantageously prevented from escaping outside through the surface of the nitride semiconductor layer and disappearing. A manufacturing method of a semiconductor device including a nitride semiconductor layer is provided. The manufacturing method includes implanting impurities into the nitride semiconductor layer, performing a first annealing on the nitride semiconductor layer at a first temperature within an atmosphere of a nitrogen atom containing gas without providing a protective film on the nitride semiconductor layer, forming the protective film on the nitride semiconductor layer after the first annealing, and after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.

Abstract: Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A first SiC layer is formed on a silicon substrate, and using a carbon containing gas, a surface of the first SiC layer is carbonized to form carbon particles on the SiC layer. Then, a diamond layer is grown on the carbonized surface, where the carbon atoms act as seed particles for growing the diamond layer. A second SiC layer is formed on the diamond layer and a semiconductor layer having III-Nitride compounds is formed on the second SiC layer. Then, the silicon substrate and the first SiC layer are removed.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: A device substrate in which no streaked morphological abnormality occurs is achieved. A GaN template substrate includes: a base substrate; and a first GaN layer epitaxially formed on the base substrate, wherein the first GaN layer has a compressive stress greater than or equal to 260 MPa that is intrinsic in an inplane direction, or a full width at half maximum of a peak representing E2 phonons of GaN near a wavenumber of 568 cm?1 in a Raman spectrum is lower than or equal to 1.8 cm?1. With all of these requirements, a device substrate includes: a second GaN layer epitaxially formed on the first GaN layer; and a device layer epitaxially formed on the second GaN layer and made of a group 13 nitride.

Abstract: A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

Abstract: In a light emitting device, a ridge section has first and second tapered sections respectively increasing in width from a center position toward first and second light exiting surfaces, and a connection area has third and fourth tapered sections respectively increasing in width from the center position toward the first and second light exiting surfaces. The outer edge angle of the connection area that specifies the third tapered section's width relative to the center line of an optical waveguide is greater than the outer edge angle of the ridge section that specifies the first tapered section's width relative to the center line. The outer edge angle of the connection area that specifies the fourth tapered section's width relative to the center line is greater than the outer edge angle of the ridge section that specifies the second tapered section's width relative to the center line.

Abstract: A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first and second substrates, a metal layer with a thickness controlled to limit surface roughness of each of the deposited metal layers to below a roughness threshold; exposing the metal layers deposited on the surface of the first and second substrates to air; directly adhering the first and second substrates by placing the deposited metal adhesion layers in contact, the surface roughness of the contacted layers being that obtained at an end of the depositing. The adhesion can be carried out in the air, at atmospheric pressure and at room temperature, without applying pressure to the assembly of the first and second substrates resulting from directly contacting the deposited metal adhesion layers.

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

Abstract: A method for producing a gallium nitride crystal includes growing a gallium nitride crystal 5 by dissolving nitrogen in a mixed melt including gallium and sodium, and collecting the gallium 55 separated from an alloy 51 including the gallium and the sodium by reacting the alloy 51 and a liquid 52 that ionizes the sodium and separating sodium ions and the gallium 55 from the alloy.

Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.

Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.

Abstract: A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode.

Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

Abstract: A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm?3 and at most equal to 2*1018 cm?3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.