Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.

Abstract: A bus bar includes a load terminal connector comprising a conductive plate that extends from a first edge to an opposite second edge and extends from a third edge to an opposite fourth edge. The third and fourth edges extend from the first edge to the second edge. The plate includes a window opening located between the first and second edges and between the third and fourth edges. The plate also includes a slot extending into the plate from the first edge to the window opening. The plate includes first and second sets of openings configured to receive connections with first and second power terminals of switch packages. The first set of openings and the second set of openings are located on opposite sides of the slot.

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

Abstract: A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.

Abstract: A control device for vehicle-mounted equipment according to the present invention includes a first sensor, a second sensor, a first microprocessor, and a second microprocessor. The second microprocessor generates a second sensor data request signal for requesting the second sensor to transmit second sensor data. The first microprocessor determines whether an abnormality has occurred in the second microprocessor based on the second sensor data or the second sensor data request signal, and based on a signal relating to information on the second microprocessor which is transmitted from a second inter-microcomputer communication unit of the second microprocessor.

Abstract: Highly conductive electrical traces formed over mechanical steps or on non-planar surfaces with linewidths of 10 to 100 ?m and a method for forming such electrical traces are disclosed. The method employs two steps, with the first step using an aerosol jet printing (AJP) process to form thin electrical traces that serve as the seed layers for the second step. The first step preferably employs multiple passes with the AJP to create multiple seed sub-layers with improved continuity and conductivity. In the second step, the seed layers are subjected to an electrodeposition process that forms the bulk of the thickness of the electrical traces. The electrodeposition process may include one, two, or three phases at corresponding low or high biases, with low biases providing denser, more highly conductive plating sub-layers, while high biases provide plating sub-layers having better gap bridging properties.

Abstract: Packages and methods of fabricating the same are provided. The package includes a first die, wherein the first die includes a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.

Abstract: A display device includes a plurality of pixels, first to nth scanning lines, and a first semiconductor film. The plurality of pixels is arranged in first to nth rows and first to mth columns. The first to nth scanning lines are electrically connected to the pixels in the respective first to nth rows. The first semiconductor film overlaps with at least one of first to kth scanning lines. A display region has a cutoff intersecting the first to nth rows, and the first semiconductor film is located in the cutoff. Each of the plurality of pixels includes a light-emitting element (OLED) and a transistor electrically connected to the OLED and having a second semiconductor film. The first semiconductor film and the second semiconductor film exist in the same layer. n and m are each a natural number larger than 1, and k is a natural number smaller than n.

Abstract: A conductive wire structure including a first conductive wire and a second conductive wire is provided. The second conductive wire is located on one side of the first conductive wire. The first conductive wire includes a first conductive wire portion and a first pad portion. The first conductive wire portion extends in a first direction and has a first end and a second end. The first pad portion is connected to the first end of the first conductive wire portion. The second conductive wire includes a second conductive wire portion and a second pad portion. The second conductive wire portion extends in a second direction and has a third end and a fourth end. The third end is adjacent to the first end, and the fourth end is adjacent to the second end. The second pad portion is connected to the fourth end of the second conductive wire portion.

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

Abstract: In radio-frequency (RF) devices integrated on semiconductor-on-insulator (e.g., silicon-based) substrates, RF losses may be reduced by increasing the resistivity of the semiconductor device layer in the vicinity of (e.g., underneath and/or in whole or in part surrounding) the metallization structures of the RF device, such as, e.g., transmission lines, contacts, or bonding pads. Increased resistivity can be achieved, e.g., by ion-implantation, or by patterning the device layer to create disconnected semiconductor islands.

Abstract: A sensor lens assembly having a non-reflow configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed to a surface of the circuit board, a sensor chip assembled to the circuit board, a plurality of wires electrically coupling the sensor chip and the circuit board, a supporting adhesive layer, and a light-permeable sheet. The circuit board has a chip-receiving slot recessed in the surface thereof. The sensor chip is arranged in the chip-receiving slot, and a top surface of the sensor chip and the surface of the circuit board have a step difference therebetween that is less than or equal to 10 ?m. The supporting adhesive layer is in a ringed shape and is disposed on the top surface of the sensor chip. The light-permeable sheet is disposed on the supporting adhesive layer and faces the sensor chip.

Abstract: A substrate processing method includes preparing a substrate, forming a plating inhibiting film and forming a plating film. In the preparing of the substrate, the substrate W which has a recess 101 formed on a front surface thereof and a seed layer 102 formed on the front surface and an inner surface of the recess is prepared. In the forming of the plating inhibiting film, the plating inhibiting film 103C is formed on an upper portion of the recess. In the forming of the plating film, the plating film 104 is formed in the recess by bringing the substrate into contact with a plating liquid after the forming of the plating inhibiting film, to thereby fill the recess with the plating film.

Abstract: A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.

Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.

Abstract: A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a second dielectric layer, and a conductive layer. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer includes a dielectric pattern. The conductive layer is disposed between the first dielectric layer and the second dielectric layer, and the conductive layer includes a first conductive pattern. The dielectric pattern has a through hole, and in a top view of the package device, the first conductive pattern and the through hole are overlapped with each other.

Abstract: The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a surface. The chip package structure includes a chip structure over the surface of the wiring substrate. The chip package structure includes an antiwarpage structure over the surface of the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure affixed to the surface of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure is electrically isolated from the chip structure.

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.

Abstract: A flexible printed circuit board and a display device including the same are provided. An embodiment of a display device includes a display panel; a first circuit board attached to a first side of the display panel in a first direction; and a second circuit board attached to a second side of the first circuit board in the first direction, wherein the first circuit board includes a first bump area overlapping the display panel and a second bump area overlapping the second circuit board, the first bump area includes a plurality of first divided board portions arranged along a second direction crossing the first direction, and the first divided board portions of the plurality of first divided board portions partially overlap each other.

Abstract: A semiconductor device incudes: a semiconductor chip that includes an active area and an outer peripheral area surrounding the active area; a metal member that includes one face including a mounting portion on which the semiconductor chip is mounted and a peripheral member surrounding the mounting portion; a joining member that connects the semiconductor chip and the metal member; and a sealing resin body. The metal member includes, as the peripheral portion, an adhesive portion that surrounds the mounting portion and adheres to the sealing resin body, and a non-adhesive portion that is placed between the mounting portion and the adhesive portion. An entire width is placed in an area overlapping the semiconductor chip in a projection view in a thickness direction of the semiconductor chip.

Abstract: A power semiconductor module comprises abase plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A method of testing an electronic device includes providing an electronic device. The electronic device includes a display layer that includes a common electrode. The electronic device also includes a sensor layer disposed on the display layer and that includes a first sensing electrode and a second sensing electrode. The first sensing electrode and the second sensing electrode cross each other and are electrically disconnected. The method further includes providing a test signal that includes a test frequency to the first sensing electrode, measuring a capacitance of a capacitor disposed between the first and second sensing electrodes based on the test signal, and testing the common electrode based on the capacitance.

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Abstract: A semiconductor package structure includes a first die, a second die disposed on the first die, and a bonding pad structure. The first die includes a semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, a passivation layer disposed on the interconnect structure, and a test pad disposed on the passivation layer. The test pad includes a contact region that extends through the passivation layer and electrically contacts the interconnect structure, and a bonding recess that overlaps with the contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate. The bonding pad structure electrically connects the first die and the second die and directly contacts at least a portion of the bonding recess.

Abstract: The present disclosure provides a semiconductor structure with an antenna and a method making the same. The semiconductor structure has an antenna substrate with a first surface and a second surface opposite to the first surface; an antenna module disposed on the first surface of the antenna substrate; and a redistribution layer disposed on the second surface of the antenna substrate. The semiconductor structure with the antenna according to the present application provides the antenna module and the redistribution layer on two opposite surfaces of the antenna substrate, the material of the antenna substrate for supporting the antenna module can be selected according to actual needs, to provide more options. Signal loss can be reduced through the selection of the antenna substrate; the redistribution layer is provided on the surface of the antenna substrate for bonding the semiconductor chips.

Abstract: The present disclosure relates to an organic light-emitting display substrate and a display device. The organic light-emitting display substrate includes a plurality of rows of sub-pixels, each of which includes first sub-pixels, second sub-pixels and third sub-pixels repeatedly arranged, and two adjacent rows of sub-pixels are arranged in a staggered manner, in every two adjacent rows of sub-pixels: a first sub-pixel in one row of sub-pixels and a second sub-pixel and a third sub-pixel that are adjacent to the first sub-pixel in the other row of sub-pixels, form a pixel unit, and white light brightness centers of the pixel units in a same row are located on a same straight line.

Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

Abstract: An object of the present invention is to provide a new electroless plating film which can prevent the diffusion of molten solder to a metal material constituting a conductor. The present invention is an electroless Co—W plating film, wherein content of W is in an amount of 35 to 58 mass % and a thickness of the film is 0.05 ?m or more.

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.

Abstract: A pixel array substrate including a substrate, multiple insulation patterns, multiple signal lines, and multiple pixel structures is provided. The insulation patterns are disposed on the substrate, and each has at least one recess structure. The signal lines are respectively disposed on the insulation patterns and are respectively filled in the at least one recess structure of one of the insulation patterns. The pixel structures are disposed on the substrate and are electrically connected to the signal lines. A pixel array substrate further including multiple conductive patterns is also disposed.

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide.

Abstract: An embodiment of the present invention provides a conductive particle used for a testing socket electrically connecting a lead of a device to be tested and a pad of a test board by being arranged between the device to be tested and the test board, wherein the conductive particle comprises a plurality of protrusions formed at equal intervals along a circumference.

Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.