Abstract: This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 ?m.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.

Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

Abstract: The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.

Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.

Abstract: A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.

Abstract: Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.

Abstract: The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: Provided is a substrate structure including: a base substrate on which a conductive pattern is formed; a first plating layer covering the conductive pattern; and a second plating layer covering the first plating layer, wherein the first plating layer includes an electroless reduction plating layer.

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.

Abstract: A tin (Sn)-based solder ball and a semiconductor package including the same are provided. The tin-based solder ball includes about 0.2 to 4 wt. % silver (Ag), about 0.1 to 1 wt. % copper (Cu), about 0.001 to 0.3 wt. % aluminum (Al), about 0.001% to 0.1 wt. % germanium (Ge), and balance of tin and unavoidable impurities. The tin-based solder ball has a high oxidation resistance.

Abstract: A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract: An interconnect assembly that operates in environments well exceeding 200° C. without degradation and/or failure. The interconnect assembly of the present invention eliminates the incompatible metal interfaces of the prior art and relies on aluminum first-metal wire to electrically connect to first-metal pads on a chip and a second-metal wire to electrically connect to second-metal plated contacts on a package. Both wire types are then electrically connected together utilizing a high temperature transition pad disposed between the chip and contacts on the package, therefore eliminating incompatible metal interfaces of the prior art.

Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Abstract: A manufacturing method of a bump structure is provided. A substrate having at least one pad and a passivation layer is provided. The passivation layer has at least one first opening exposing the pad. An insulating layer is formed on the passivation layer. The insulating layer has at least one second opening located above the first opening. A metal layer is formed on the insulating layer. The metal layer electrically connects the pad through the first and second openings. A first bump is formed in the first and second openings. A second bump is formed on the first bump and a portion of the metal layer. The metal layer not covered by the second bump is partially removed by using the second bump as a mask, so as to form at least one UBM layer. The first bump is completely covered by the UBM layer and the second bump.

Abstract: An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.

Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: (1) Forming a plurality of lower electrodes over a substrate. (2) Forming a first stop film over the lower electrodes. (3) Forming a filling layer over the first stop film. (4) Forming a second stop film over the filling layer. (5) Forming a first interlayer insulating layer over the second stop film. (6) Forming a plurality of upper electrodes over the first interlayer insulating layer. (7) Forming a second interlayer insulating layer over the upper electrodes. (8) Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. (9) Forming a contact ball in the cavity.

Abstract: A first transistor group, a second transistor group, and an electrode pad are formed on a semiconductor substrate. A first protective film is formed so as to cover the semiconductor substrate except for an upper region of the electrode pad. The second protective film which generates a stress in a projecting direction is formed so as to cover the first protective film except for an upper region of the first transistor group. A transistor ability of the first transistor group is varied to be relatively higher due to a presence of the second protective film, based on a transistor ability of the second transistor group, as a reference.

Abstract: Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.

Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.

Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.

Abstract: A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.

Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.

Abstract: A bonding structure and a copper bonding wire for semiconductor device include a ball-bonded portion formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.

Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.

Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.