Abstract: A mounting member includes: an insulating substrate, a first die pad unit, first and second terminals. The insulating substrate has a rectangular first surface, a second surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A through hole is provided from the first surface to the second surface. The first die pad unit is provided on the first surface. The first terminal has a conductive region covering the first side surface, the first surface, and the second surface. The second terminal has a conductive region covering the second side surface and the second surface, connected to the first die pad unit by conductive material provided in the through hole or on a side wall of the through hole. The first die pad unit, the first terminal, and the second terminal are apart from one another.

Abstract: The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations.

Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.

Abstract: Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package (4) includes a die pad (61), a source lead (63), a first MOSFET (11), and a first Schottky barrier diode (21). A source electrode (11S) of the first MOSFET (11), an anode electrode (21A) of the first Schottky barrier diode (21), and the source lead (63) are electrically connected by the bonding wire (31), one end of which is bonded to the source electrode (11S) of the first MOSFET (11), the other end of which is bonded to the source lead (63), and the center of which is bonded to the anode electrode (21A) of the first Schottky barrier diode (21).

Abstract: A semiconductor device includes lands having an NSMD (non-solder mask defined) structure for mounting thereon solder balls placed in an inner area of a chip mounting area. The lands for mounting thereon solder balls are placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view. The semiconductor device is mounted on a mounting substrate with the balls.

Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.

Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.

Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.

Abstract: A method for manufacturing a chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material.

Abstract: Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.

Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.

Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Abstract: A method for fabricating a substrate having transferable chiplets includes forming a photo-sensitive adhesive layer on a process side of a source substrate including active components or on a patterned side of a transparent intermediate substrate. The intermediate substrate is brought into contact with the source substrate to adhere the active components on the process side to the patterned side of the intermediate substrate via the photo-sensitive adhesive layer therebetween. Portions of the source substrate opposite the process side thereof are removed to singulate the active components. Portions of the photo-sensitive adhesive layer are selectively exposed to electromagnetic radiation through the intermediate substrate to alter an adhesive strength thereof. Portions of the photo-sensitive adhesive layer having a weaker adhesive strength are selectively removed to define breakable tethers comprising portions of the adhesive layer having a stronger adhesive strength.

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract: A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a substrate, and wire bonding the die to the substrate. The die and wire bonds are encapsuated, and the encapsulated device is singulated. The wire bonds are severed during the singulation step, and thereafter the severed wire bonds are connected to the substrate by external connectors on one or more surfaces of the molding compound.

Abstract: An apparatus includes at least a first integrated circuit (IC) and a wafer-fabricated space transformer (ST). The IC includes bonding pads of a first inter-pad pitch on a bottom surface. The ST includes a top surface having bonding pads of the first inter-pad pitch, and at least a portion of the bonding pads of the first IC are bonded to the bonding pads of the top surface. The ST includes a bottom surface having bonding pads of a second inter-pad pitch, at least one dielectric insulating layer between the top surface and the bottom surface, and conductive interconnect in the dielectric layer configured to provide electrical continuity between the bonding pads of the top surface and the bonding pads of the bottom surface.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Abstract: Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Abstract: When a conductive post is bonded to a bonding target member such as a semiconductor chip or an insulating substrate with conductive patterns by using metal nanoparticles, a strong bonding layer can be obtained by forming a bottom surface of the distal end of the conductive post in a concave shape.

Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.

Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.

Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.

Abstract: A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.

Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

Abstract: An electronic device 1 has a first semiconductor substrate 2 on which a bonding projection section 42 is projected via an insulation film 41, a second semiconductor substrate 3 that is bonded by welding the bonding projection section 42 of the first semiconductor substrate 2 via conductive bonding material, a through hole 54 that is formed to penetrate the bonding projection section 42 and the insulation film 41 in a bonding direction, and a conduction wiring section 44 that is formed by the conductive bonding material filled in the through hole 54 at a time of bonding by welding and conducts the first semiconductor substrate 2 with the second semiconductor substrate 3 to have same electric potential.

Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Abstract: Stacking balls are formed on ball terminals prior to application of an underfill under a flip chip mounted electronic component. The underfill is then applied and directly contacts and at least partially encloses an inner row of the stacking balls closest to and directly adjacent the flip chip mounted electronic component. By forming the stacking balls prior to the application of the underfill, contamination of the ball terminals by the underfill is avoided. This allows the spacing between the ball terminals and the electronic component to be minimized.

Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: A power module includes a substrate having an electrically insulative member with opposing first and second metallized sides and one or more semiconductor die attached to the first metallized side of the substrate. A plurality of thermally conductive structures are laterally spaced apart from one another and individually attached directly to the second metallized side of the substrate so that the plurality of thermally conductive structures extend outward from the second metallized side.

Abstract: Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed.

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.

Abstract: A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.

Abstract: [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.