Abstract: A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: A pressure sensor package is provided that reduces the occurrence of micro gaps between molding material and metal contacts that can store high-pressure air. The present invention provides this capability by reducing or eliminating interfaces between package molding material and metal contacts. In one embodiment, a control die is electrically coupled to a lead frame and then encapsulated in molding material, using a technique that forms a cavity over a portion of the control die. The cavity exposes contacts on the free surface of the control die that can be electrically coupled to a pressure sensor device using, for example, wire bonding techniques. In another embodiment, a region of a substrate can be encapsulated in molding material, using a technique that forms a cavity over a sub-portion of the substrate that includes contacts. A pressure sensor device can be electrically coupled to the exposed contacts.

Abstract: A process for forming a heat sink on a semiconductor package at the wafer level stage of manufacture is disclosed. A semiconductor component wafer, prior to separation into separate component packages, is covered on one side with a resin metal foil layer. The resin foil layer is patterned by laser ablation to define the heat sink locations, and then a thermal paste is applied over the patterned layer. The thermal conductive paste is hardened to form the heat sinks. The wafer can then be separated into packages.

Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a package body; a plurality of electrodes including a first electrode on the package body; a paste member on the first electrode and including inorganic fillers and metal powder; and a semiconductor device die-bonded on the paste member, wherein a die-bonding region of the first electrode includes a paste groove having a predetermined depth and the paste member is formed in the paste groove.

Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.

Abstract: To provide a semiconductor device having suspension leads with less distortion. In QFN having a plurality of external terminal portions at the periphery of the bottom surface of a sealing body, a plurality of leads is linked to a plurality of long suspension leads of the QFN at an intermediate portion thereof or at between the intermediate portion and a position near the die pad. These long suspension leads are each supported by these leads, making it possible to suppress distortion of each of the suspension leads in a wire bonding step or molding step in the fabrication of the QFN.

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads.

Abstract: A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar), The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer.

Abstract: A method produces a bonding pad for thermocompression bonding. The method includes providing a carrier material having semiconductor structures, wherein an outermost edge layer of the carrier material is a wiring metal layer configured to make electrical contact with the semiconductor structures. The method also includes depositing a single-layered bonding metal layer directly on a surface of the wiring metal layer to produce the bonding pad.

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract: A wafer-level semiconductor package method comprising the step of providing a first wafer comprising a plurality of first dies each having a first, a second and a third electrodes formed on its front surface; attaching a second die having a fourth and a fifth electrodes formed on its front surface and a sixth electrode formed at its back surface onto each of the first die of the first wafer with the sixth electrode at the back surface of the second die attached and electrically connected to the second electrode at the front surface of the first die; and cutting the first wafer to singulate individual semiconductor packages.

Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.

Abstract: A micromechanical assembly for bonding semiconductor substrates includes a semiconductor substrate having a chip pattern having a plurality of semiconductor chips, each having a functional region and an edge region surrounding the functional region. There is a bonding frame made of a bonding alloy made from at least two alloy components in the edge region, spaced apart from the functional region. Within the part of the edge region surrounding the bonding frame between the bonding frame and the functional region, there is at least one stop frame made of at least one of the alloy components, which is configured such that when a melt of the bond alloy contacts the stop frame during bonding, the bonding alloy solidifies.

Abstract: A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material.

Abstract: Stacking balls are formed on ball terminals prior to application of an underfill under a flip chip mounted electronic component. The underfill is then applied and directly contacts and at least partially encloses an inner row of the stacking balls closest to and directly adjacent the flip chip mounted electronic component. By forming the stacking balls prior to the application of the underfill, contamination of the ball terminals by the underfill is avoided. This allows the spacing between the ball terminals and the electronic component to be minimized.

Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Abstract: To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates.

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.

Abstract: A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer.

Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.

Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers.

Abstract: A packaged semiconductor device comprises a package substrate comprising a first package substrate contact and a second package substrate contact, and a semiconductor die over the package substrate. The semiconductor device further includes electrical connections between signal contact pads of the die and the package substrate, and a heat spreader that comprises a first heat spreader portion which is electrically connected to a first signal contact pad and the first package substrate contact and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer is positioned between the first and second heat spreader portions.

Abstract: An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located.

Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Abstract: A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Abstract: A semiconductor device wherein a semiconductor element made of Si or Si group material mounted on a substrate, the semiconductor element is mounted on the substrate and the semiconductor element is bonded to a silver bonding material via a oxide film formed on the semiconductor element. The bonding material comprising silver oxide particles having an average particle size of 1 nm to 50 nm and an organic reducing agent is used for bonding in air, which gives a high bonding strength to the oxide on the semiconductor element.

Abstract: To suppress peeling of an Au pad for external coupling provided in a rewiring containing Cu as a main component. On the surface of a rewiring including a two-layer film in which a first Ni film is laminated on the top of a Cu film, a pad to which a wire is coupled is formed. The pad includes a two-layer film in which an Au film is laminated on the top of a second Ni film and formed integrally so as to cover the top surface and the side surface of the rewiring. Due to this, the area of contact between the rewiring and the pad increases, and therefore, the pad becomes difficult to be peeled off from the rewiring.

Abstract: A low temperature wafer bonding method and a bonded structure are provided. The method includes: providing a first substrate having a plurality of metal pads and a first dielectric layer close to the metal pads, where the metal pads and the first dielectric layer are on a top surface of the first substrate; providing a second substrate having a plurality of semiconductor pads and a second dielectric layer close to the semiconductor pads, where the semiconductor pads and the second dielectric layer are on a top surface of the second substrate; disposing at least one of the metal pads in direct contact with at least one of the semiconductor pads, and disposing the first dielectric layer in direct contact with the second dielectric layer; and bonding the metal pads with the semiconductor pads, and bonding the first dielectric layer with the second dielectric layer.

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components.

Abstract: A power module includes a substrate having an electrically insulative member with opposing first and second metallized sides and one or more semiconductor die attached to the first metallized side of the substrate. A plurality of thermally conductive structures are laterally spaced apart from one another and individually attached directly to the second metallized side of the substrate so that the plurality of thermally conductive structures extend outward from the second metallized side.

Abstract: A package is connected at a first side to a printed circuit board and with a die fixed to it on a second side opposite to the first side. The package has an integrated pre-match circuit to provide an impedance match for a signal to be sent to a circuit external to the package. The signal has a predetermined main frequency component. The pre-match circuit has a pair of transmission lines and a pair of stubs on a predetermined layer of the package and connected to the pair of transmission lines. The pair of stubs have a length such as to form a short circuit for an harmonic frequency of the main frequency component in the signal.

Abstract: A method for attaching a metal surface to a carrier is provided, the method including: depositing a porous layer over at least one of a metal surface and a side of a carrier; and attaching the at least one of a metal surface and a side of a carrier to the porous layer by bringing a material into pores of the porous layer, resulting in the material forming an interconnection between the metal surface and the carrier.

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.