Ii-vi Compound Patents (Class 257/78)
  • Patent number: 8278656
    Abstract: The subject of the invention is a substrate that can be used as a substrate for the epitaxial growth of layers based on gallium nitride and comprising a support material (11, 21) coated on at least one of its faces with at least one multilayered stack comprising at least one zinc-oxide-based layer (13, 24). The substrate is coated with a semiconductor structure of III-N or II-VI type, and it is characterized in that placed between the support material (11, 21) and said at least one zinc-oxide-based layer (13, 24) is at least one intermediate layer (12, 23) comprising oxides with at least two elements chosen from tin (Sn), zinc (Zn), indium (In), gallium (Ga) and antimony (Sb).
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: October 2, 2012
    Assignee: Saint-Gobain Glass France
    Inventors: Eric Mattmann, Pascal Reutler, Fabien Lienhart
  • Patent number: 8274078
    Abstract: Provided is an oxynitride semiconductor comprising a metal oxynitride. The metal oxynitride contains Zn and In and at least one element selected from the group consisting of Ga, Sn, Mg, Si, Ge, Y, Ti, Mo, W, and Al. The metal oxynitride has an atomic composition ratio of N, N/(N+O), of 7 atomic percent or more to 80 atomic percent or less.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: September 25, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Naho Itagaki, Tatsuya Iwasaki, Masatoshi Watanabe, Toru Den
  • Patent number: 8274138
    Abstract: A high quality II-VI semiconductor nanowire is disclosed. A plurality of II-VI semiconductor nanowires is provided, with each being fixed to a support. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Eastman Kodak Company
    Inventor: Keith B. Kahen
  • Patent number: 8257999
    Abstract: A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO2 mask into stripes oriented in the gallium nitride <1 100> or <11 20> direction; (3) growing epitaxial lateral overgrowth of (ELO) gallium nitride layers by controlling the facet planes via choosing the growth temperature and the reactor; (4) depositing zinc oxide films on facets ELO gallium nitride templates by chemical vapor deposition (CVD). Zinc oxide crystal of high quality with a reduced number of crystal defects can be grown on a gallium nitride template. This method can be used to fabricate zinc oxide films with low dislocation density lower than 104/cm?2, which will find important applications in future electronic and optoelectronic devices.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 4, 2012
    Assignee: National University of Singapore
    Inventors: Soo Jin Chua, Hailong Zhou, Jianyi Lin, Hui Pan
  • Patent number: 8232580
    Abstract: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as to be on/off-controlled by a control signal from the photodiode.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: July 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiaki Nozaki
  • Patent number: 8193543
    Abstract: Light emitting systems are disclosed. The light emitting system includes an LED that emits light at a first wave-length. A primary portion of the emitted first wavelength light exits the LED from a top surface of the LED that has a minimum lateral dimension Wmin. The remaining portion of the emitted first wavelength light exits the LED from one or more sides of the LED that has a maximum edge thickness Tmax (122, 124). The ratio Wmin/Tmax is at least 30. The light emitting system further includes a re-emitting semiconductor construction that includes a semiconductor potential well. The re-emitting semiconductor construction receives the first wavelength light that exits the LED from the top surface and converts at least a portion of the received light to light of a second wavelength.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 5, 2012
    Assignee: 3M Innovative Properties Company
    Inventors: Catherine A. Leatherdale, Michael A. Haase, Todd A. Ballen
  • Patent number: 8193537
    Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: June 5, 2012
    Assignee: SS SC IP, LLC
    Inventor: Michael S. Mazzola
  • Patent number: 8174024
    Abstract: In one aspect, a device includes a gallium nitride (GaN) layer, a first diamond layer disposed on the GaN layer, a gate structure disposed in contact with the GaN layer and the first diamond layer, and a second diamond layer having a first thermal conductivity and disposed on a second surface of the GaN layer. The gate and the first diamond layer are disposed on a first surface of the GaN layer opposite the second surface of the GaN layer.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: May 8, 2012
    Assignee: Raytheon Company
    Inventors: Ralph Korenstein, Steven D. Bernstein, Stephen J. Pereira
  • Patent number: 8164101
    Abstract: A light-emitting device includes a light-emitting portion and an oxygen concentration control portion. The light-emitting portion includes a surface. The light-emitting portion emits light with an intensity corresponding to an oxygen concentration on the surface when receiving light energy. The oxygen concentration control portion controls the oxygen concentration on the surface of the light-emitting portion.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: April 24, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takashi Morikawa, Kei Shimotani
  • Patent number: 8148731
    Abstract: Semiconductor films and structures, such as films and structures utilizing zinc oxide or other metal oxides, and processes for forming such films and structures, are provided for use in metal oxide semiconductor light emitting devices and other metal oxide semiconductor devices, such as ZnO based semiconductor devices.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: April 3, 2012
    Assignee: Moxtronics, Inc.
    Inventors: Yungryel Ryu, Tae-seok Lee, Henry W. White
  • Patent number: 8129717
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8129260
    Abstract: A semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. At least one amorphous region and at least one crystalloid region are formed in the first semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer and is crystal-grown from the at least one crystalloid region. A method of manufacturing a semiconductor substrate includes preparing a growth substrate; crystal-growing the first semiconductor layer on the growth substrate; forming the at least one amorphous region and the at least one crystalloid region in the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer using the at least one amorphous region as a mask and the at least one crystalloid region as a seed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 6, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Ho-sun Paek, Youn-joon Sung, Kyoung-ho Ha, Joong-kon Son, Sung-nam Lee
  • Patent number: 8119513
    Abstract: A method for making a cadmium sulfide layer is provided. The method includes a number of steps including providing a substrate and disposing a layer containing cadmium on the substrate followed by sulfurization of the cadmium-containing layer.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 21, 2012
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Scott Feldman-Peabody, Robert Dwayne Gossman
  • Patent number: 8097885
    Abstract: Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has a composition represented by a Cu2—Zn—IV—S4 type, in which the IV is at least one of Ge and Si. The light emitting film includes the light emitting material and the compound semiconductor film laminated on a substrate in the stated order.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 17, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Oike, Tatsuya Iwasaki
  • Patent number: 8097886
    Abstract: An organic electroluminescence device which can prevent the deterioration thereof attributed to moisture by preventing a desiccant from influencing organic electroluminescence elements is provided. The organic electroluminescence device includes: first and second substrates which are arranged to face each other in an opposed manner with a gap therebetween; organic electroluminescence elements which are formed on a first surface of the first substrate which faces the second substrate in an opposed manner; a desiccant which is formed on a second surface of the second substrate which faces the first substrate in an opposed manner; and a resin which is adhered to the first and second surfaces and covers the desiccant and the organic electroluminescence elements.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 17, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Satoru Kase, Yoshinori Ishii, Eiji Matsuzaki
  • Patent number: 8093095
    Abstract: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or transition region (12). A particular application of the device is for a radiation detector.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 10, 2012
    Assignee: Kromek Limited
    Inventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
  • Patent number: 8093589
    Abstract: In a thin film transistor (1), a gate insulating layer (4) is formed on a gate electrode (3) formed on an insulating substrate (2). Formed on the gate insulating layer (4) is a semiconductor layer (5). Formed on the semiconductor layer (5) are a source electrode (6) and a drain electrode (7). A protective layer (8) covers them, so that the semiconductor layer (5) is blocked from an atmosphere. The semiconductor layer (5) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: January 10, 2012
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Toshinori Sugihara, Hideo Ohno, Masashi Kawasaki
  • Patent number: 8093671
    Abstract: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or transition region (12). A particular application of the device is for a radiation detector.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: January 10, 2012
    Assignee: Kromek Limited
    Inventors: Arnab Basu, Max Robinson, Benjamin John Cantwell, Andy Brinkman
  • Patent number: 8080824
    Abstract: A semiconductor material structure includes at least one region capable of generating electrons and holes each having an associated mean kinetic energy during operation. A material layer in proximity to the region provides an associated potential energy larger than the mean kinetic energy associated with the generated electrons and the mean kinetic energy associated with the holes.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: December 20, 2011
    Assignee: Academia Sinica
    Inventors: Kuei-Hsien Chen, Chien-Hung Lin, Chia-Wen Hsu, Li-Chyong Chen
  • Patent number: 8076677
    Abstract: A semiconductor light emitting device includes a semiconductor light emitting element, a lead electrically connected to the semiconductor light emitting element, and a resin package covering the semiconductor light emitting element and part of the lead. The resin package includes a lens facing the semiconductor light emitting element. The lead includes an exposed portion that is not covered by the resin package. The exposed portion includes a first portion and a second portion, where the first portion has a first mount surface oriented backward along the optical axis of the lens, and the second portion has a second mount surface oriented perpendicularly to the optical axis of the lens.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: December 13, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasunori Hata, Masahiko Kobayakawa
  • Patent number: 8071482
    Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: December 6, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasuyuki Kawada
  • Publication number: 20110269261
    Abstract: Methods for protecting a cadmium sulfide layer on a substrate are provided. The method can include sputtering a cadmium sulfide layer onto a substrate from a cadmium sulfide target at a sputtering pressure (e.g., about 10 mTorr to about 150 mTorr), and sputtering a cap layer directly on the cadmium sulfide layer. The cap layer can be sputtered directly onto the cadmium sulfide layer without breaking vacuum of the sputtering pressure. Methods are also provided for manufacturing a cadmium telluride based thin film photovoltaic device through depositing a cadmium sulfide layer on a substrate, depositing a cap layer directly on the cadmium sulfide layer, heating the substrate to sublimate at least a portion of the cap layer from the cadmium sulfide layer, and then depositing a cadmium telluride layer on the cadmium sulfide layer. An intermediate substrate for forming a cadmium telluride based thin-film photovoltaic device is also provided.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Jennifer Ann Drayton, Richard Ernest Demaray
  • Patent number: 8049225
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8030663
    Abstract: A semiconductor device including thin film transistors having high electrical properties and reliability is proposed. Further, a method for manufacturing the semiconductor devices with mass productivity is proposed. The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8013323
    Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: September 6, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Chul Choi
  • Patent number: 8008694
    Abstract: A light source with enhanced brightness includes an angle-selective optical filter and a light emitting diode (LED) having a high reflective layer. The angle-selective filter is located on the top surface of emitting diode to pass lights at specified angles. According to one embodiment, the angle-selective filter includes index-alternating layers. With a reflective polarizer, the light source can produce polarized light with enhanced brightness.
    Type: Grant
    Filed: September 22, 2007
    Date of Patent: August 30, 2011
    Assignee: YLX, Ltd.
    Inventors: Li Xu, Yi Li
  • Patent number: 7999346
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: August 16, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7989237
    Abstract: Silicon substrates are applied to the package structure of solid-state lighting devices. Wet etching is performed to both top and bottom surfaces of the silicon substrate to form reflecting cavity and electrode access holes. Materials of the reflecting layer and electrode can be different from each other whose preferred materials can be chosen in accordance with a correspondent function. Formation of the electrode can be patterned by an etching method or a lift-off method.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 2, 2011
    Assignee: Advances Optoelectronic Technology, Inc.
    Inventors: Wen Liang Tseng, Lung Hsin Chen
  • Patent number: 7989261
    Abstract: In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer. In another aspect, a device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 2, 2011
    Assignee: Raytheon Company
    Inventors: Ralph Korenstein, Steven D. Bernstein, Stephen J. Pereira
  • Patent number: 7972931
    Abstract: The present invention relates to a method of manufacturing thin-film transistors using nanoparticles and thin film transistors manufactured by the method. A hydrophilic buffer layers are deposited on the substrates to facilitate formation of nanoparticle films. Sintered nanoparticles are used as an active layer and dielectric materials of high dielectric coefficient are also used as a gate dielectric layer to form a top gate electrode on the gate dielectric layer, thereby enabling low-voltage operation and low-temperature fabrication.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: July 5, 2011
    Assignee: Korea University Industrial & Academic Collaboration Foundation
    Inventors: Sangsig Kim, Kyoung-Ah Cho, Dong-Won Kim, Jae-Won Jang
  • Publication number: 20110140129
    Abstract: Light emitting systems are disclosed. The light emitting system includes an LED that emits light at a first wavelength and includes a pattern that enhances emission of light from a top surface of the LED and suppresses emission of light from one or more sides of the LED. The light emitting system further includes a re-emitting semiconductor construction that includes a II-VI potential well. The re-emitting semiconductor construction receives the first wavelength light that exits the LED and converts at least a portion of the received light to light of a second wavelength. The integrated emission intensity of all light at the second wavelength that exit the light emitting system is at least 4 times the integrated emission intensity of all light at the first wavelength that exit the light emitting system.
    Type: Application
    Filed: August 18, 2009
    Publication date: June 16, 2011
    Inventors: Catherine A. Leatherdale, Todd A. Ballen, Thomas J. Miller
  • Publication number: 20110140128
    Abstract: Light emitting systems are disclosed. The light emitting system includes an LED that emits light at a first wave-length. A primary portion of the emitted first wavelength light exits the LED from a top surface of the LED that has a minimum lateral dimension Wmin. The remaining portion of the emitted first wavelength light exits the LED from one or more sides of the LED that has a maximum edge thickness Tmax (122, 124). The ratio Wmin/Tmax is at least 30. The light emitting system further includes a re-emitting semiconductor construction that includes a semiconductor potential well. The re-emitting semiconductor construction receives the first wavelength light that exits the LED from the top surface and converts at least a portion of the received light to light of a second wavelength.
    Type: Application
    Filed: August 18, 2009
    Publication date: June 16, 2011
    Inventors: Catherine A. Leatherdale, Michael A. Haase, Todd A. Ballen
  • Patent number: 7956360
    Abstract: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: June 7, 2011
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Benjamin A. Haskell, Melvin B. McLaurin, Steven P. DenBaars, James Stephen Speck, Shuji Nakamura
  • Patent number: 7951639
    Abstract: A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO2 mask into stripes oriented in the gallium nitride <1 100> or <11 20> direction; (3) growing epitaxial lateral overgrowth of (ELO) gallium nitride layers by controlling the facet planes via choosing the growth temperature and the reactor; (4) depositing zinc oxide films on facets ELO gallium nitride templates by chemical vapor deposition (CVD). Zinc oxide crystal of high quality with a reduced number of crystal defects can be grown on a gallium nitride template. This method can be used to fabricate zinc oxide films with low dislocation density lower than 104/cm?2, which will find important applications in future electronic and optoelectronic devices.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: May 31, 2011
    Assignee: National University of Singapore
    Inventors: Soon Jin Chua, Hailong Zhou, Jianyi Lin, Hui Pan
  • Publication number: 20110121319
    Abstract: Light emitting devices and methods of fabricating the same are disclosed. The light emitting device includes a light emitting diode (LED) that emits blue or UV light and is attached to a semiconductor construction. The semiconductor construction includes a re-emitting semiconductor construction that includes at least one layer of a II-VI compound and converts at least a portion of the emitted blue or UV light to longer wavelength light. The semiconductor construction further includes an etch-stop construction that includes an AlInAs or a GaInAs compound. The etch-stop is capable of withstanding an etchant that is capable of etching InP.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 26, 2011
    Inventors: Michael A. Haase, Thomas J. Miller, Xiaoguang Sun
  • Patent number: 7947999
    Abstract: A luminescent device including a die pad lead composed of an inner lead and an outer lead, a case for uniting the inner lead, a light emitting diode chip mounted on a first predetermined position of one main surface of the inner lead, and a transparent sealing material portion for sealing the light emitting diode chip and a part of the one main surface. The case seals the inner lead other than an area sealed by the transparent sealing material portion, and the inner lead of the die pad lead has bending portions at least two places including a first bending portion and a second bending portion. A rear of the first predetermined position in the inner lead of the die pad lead is exposed outside the case, and the second bending portion is formed in the case so that the outer lead extends from a side of the case.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taizo Tomioka, Takahiro Suzuki, Hiroyuki Tokubo, Yukinori Aoki
  • Patent number: 7915747
    Abstract: A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Matsushita
  • Patent number: 7915606
    Abstract: A semiconductor light emitting device including a substrate including a plurality of discrete and separated protruding reflective patterns protruding from the substrate and including a valley; a first semiconductor layer on the substrate and covering the reflective patterns; a gap formed in the valley of a corresponding reflective pattern between the substrate and the first semiconductor layer; an active layer on the first semiconductor layer; and a second semiconductor layer on the active layer.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 29, 2011
    Assignee: LG Electronics Inc.
    Inventors: Bum Chul Cho, Seung Hyun Yang
  • Patent number: 7915149
    Abstract: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106 ?·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: March 29, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Fumitaka Sato, Yoshiki Miura, Akinori Koukitu, Yoshinao Kumagai
  • Patent number: 7897976
    Abstract: The invention of this application is a field-effect transistor type light-emitting device having an electron injection electrode, i.e. a source electrode, a hole injection electrode, i.e. a drain electrode, an emission active member disposed between the source electrode and the drain electrode so as to contact with both electrodes, and a field application electrode, i.e. a gate electrode, for inducing electrons and holes in the emission active member, which is disposed in the vicinity of the emission active member via an electrically insulating member or an insulation gap. The emission active member is made of an inorganic semiconductor material having both an electron transporting property and a hole transporting property.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: March 1, 2011
    Assignee: Hoya Corporation
    Inventors: Hiroshi Kawazoe, Satoshi Kobayashi, Yuki Tani, Hiroaki Yanagita
  • Patent number: 7880175
    Abstract: Disclosed herein is an ultraviolet (UV) light-blocking composition comprising a metal nanoparticle that absorbs and blocks a UV light wavelength using a surface plasmon-absorbing wavelength, and a dielectric. The UV light-blocking composition is capable of absorbing and blocking a UV light wavelength or, a specific wavelength, using the surface plasmon-absorbing wavelength of the metal nanoparticle or, the plasmon-absorbing wavelength transited by the dielectric, thereby demonstrating increased visibility when applied to an image display apparatus such as a mobile phone, and the like.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: February 1, 2011
    Assignee: Samsung Advanced Institute of Technology
    Inventors: Hyeon Jin Shin, Jae Young Choi, In Yong Song, Dong Kee Yi, Seong Jae Choi, Seon Mi Yoon
  • Patent number: 7868334
    Abstract: A semiconductor light emitting device includes a semiconductor light emitting element, a lead electrically connected to the semiconductor light emitting element, and a resin package covering the semiconductor light emitting element and part of the lead. The resin package includes a lens facing the semiconductor light emitting element. The lead includes an exposed portion that is not covered by the resin package. The exposed portion includes a first portion and a second portion, where the first portion has a first mount surface oriented backward along the optical axis of the lens, and the second portion has a second mount surface oriented perpendicularly to the optical axis of the lens.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasunori Hata, Masahiko Kobayakawa
  • Patent number: 7847297
    Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: December 7, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Jeffrey N Miller, David P Bour, Virginia M Robbins, Steven D Lester
  • Patent number: 7834343
    Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: November 16, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sung Chul Choi
  • Patent number: 7821015
    Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 26, 2010
    Assignee: SemiSouth Laboratories, Inc.
    Inventor: Michael S. Mazzola
  • Patent number: 7803669
    Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hwan Cho, Bo Sung Kim, Keun Kyu Song
  • Patent number: 7700959
    Abstract: A semiconductor light-emitting device capable of obtaining a high light reflectance through the use of a high-reflection metal layer formed on the side of an electrode on one side and capable of preventing migration of atoms from the high-reflectance metal layer is provided. Semiconductor layers of the opposite conduction types are formed on the opposite sides of an active layer, and an ohmic contact layer being a thin film for contriving a decrease in contact resistance, a transparent and conductive layer, and a high-reflection metal layer for reflecting light generated in the active layer are sequentially layered on one of the semiconductor layers. Since the transparent conductive layer functions also as a barrier layer and it transmits light, a high light take-out efficiency can be obtained through the reflection at the high-reflectance metal layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 20, 2010
    Assignee: Sony Corporation
    Inventors: Jun Suzuki, Masato Doi, Hiroyuki Okuyama, Goshi Biwa
  • Patent number: 7696073
    Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: April 13, 2010
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Tetsuya Yamamoto, Atsutoshi Arakawa, Kenji Sato, Toshiaki Asahi
  • Publication number: 20100084664
    Abstract: A semiconductor structure includes a substrate which may be formed from a ZnS single crystal of wurtzite (2H) structure with a predetermined crystal orientation, and which has a first surface and a second surface. The structure includes a layer of a group III-nitride crystalline material deposited as an epitaxial layer on the first surface of the substrate. In one embodiment, the group III-nitride deposit is epitaxially grown using a MOCVD (or MOVPE) technique or a HVPE technique or a combination thereof. There may be a mask and/or a buffer layer on the first surface and/or a protective layer on the second surface.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 8, 2010
    Applicant: FAIRFIELD CRYSTAL TECHNOLOGY, LLC
    Inventor: Shaoping Wang
  • Patent number: RE42770
    Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 4, 2011
    Assignee: Nichia Corporation
    Inventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho