Abstract: The invention relates to a semiconductor device of the type sealed in glass, comprising a silicon semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition metal by means of a bonding layer, the bonding layer comprising a quantity of aluminum in the range between 7 and 15 wt. % and a quantity of silver in the range between 85 and 93 wt. %.
Abstract: A packaging material for electronic components is provided which inhibits the cracking of a passivation film on an encapsulated chip and inhibits the breaking of an interconnecting metallization pattern in a chip of an electronic component and meets the miniaturization trend for electronic components. The packaging material includes: a resin, and 80% to 93% by weight, relative to the total amount of the packaging material, of a filler made up of particles having an average particle size of 30 .mu.m or less, at least 90% by weight of which are spherically shaped or have rounded ends and/or edges.
Abstract: This invention relates to metal-containing inserts, such as transformers, that are encapsulated, via compression molding processes, with at least one wet lay thermoplastic sheet material and that do not experience significant visible cracking during heat cycling.
Type:
Grant
Filed:
October 21, 1996
Date of Patent:
November 18, 1997
Assignee:
E. I. du Pont de Nemours and Company
Inventors:
M. Lana Sheer, Lloyd Fox, John Carl Solenberger
Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.
Type:
Grant
Filed:
March 12, 1996
Date of Patent:
October 28, 1997
Assignee:
Micron Technology, Inc.
Inventors:
Warren M. Farnworth, Salman Akram, Alan G. Wood
Abstract: A semiconductor device comprises a plurality of wiring formed on a lower insulating film to be spaced apart from each other, dummy patterns formed on the lower insulating layer between the plurality of wiring and spaced apart from each other, and an upper insulating layer formed to cover the plurality of wiring and the dummy patterns and having cavities formed in regions between the plurality of wiring and the dummy patterns.
Abstract: This invention aims at providing a glass package type capacitive element having a high reliability and a high resistance to heat and mechanical impact. In the glass package, a semiconductor device (2) is connected with a lead (5) through a conductor (8) having a bent structure.
Abstract: An integrated circuit package, and integrated circuit assembly having such a package, includes a base portion and a cover portion which cooperatively enclose an integrated circuit chip. The base and cover portions are formed of composite material and have matching coefficients of thermal expansion. Because the base and cover portions each match the other's thermal expansions and contractions, no stresses are generated in the package from heating and cooling during and following operation of the integrated circuit chip, and no such thermally produced physical stresses are transferred to the circuit chip to shorten its life. A version of the package includes plural lamina, and may include facial metallic coating layers on the lamina for shielding, electromagnetic shielding, and electrical interconnection of the integrated circuit chip. Another version of the package utilizes the facial metallic coating layers to join portions of the package by soldering.
Abstract: A semiconductor device has a semiconductor chip and a ceramic envelope consisting of a base portion and a sealing portion sealing the chip, and has good high-speed operability, radiation properties and electric characteristics. Leads made of Cu and electrically connected to the semiconductor chip are held between the base portion and the sealing portion, and have anchor holes formed in the portions thereof held therebetween. A glass-based adhesive is coated in the anchor holes, between the held portions of the leads and the base portion, and between the held portions and the sealing portion.
Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.
Abstract: A highly transparent film having high strength, suitable extensibility, high weather resistance, low moisture absorption and so on is disclosed, which consists mainly of EVAT. And also various laminates making the most of the above properties of the film are disclosed, which comprise the EVAT interposed between two inorganic material sheets, two organic material sheets, or an inorganic material sheet and an organic material sheet.
Abstract: In a semiconductor device in which the surface of a semiconductor substrate which was subjected to impurity diffusion process, and includes a multilayer metal interconnection layer which is formed on top of it by alternately laminating a metal wiring layer and an interlayer insulating film, the present semiconductor device is characterized in that in a lower layer metal wiring layer there is provided a dummy wiring stripe which is arranged in parallel to two wiring stripes that are formed away from other wiring stripes at a space according to design rules. The width of the wiring stripe is augmented effectively due to the presence of the dummy stripe, and the holding quantity of the material of the coating film which constitutes a part of the interlayer insulating film is increased.
Abstract: Lead frames, in which at least one part of the surface of a metal member which is a part of the lead frame is provided with an anodic oxide film of copper or a copper alloy, and in which a member composed substantially of a resin film or a resin plate is connected to the lead frame through this anodic oxide film by gluing or pressing under heat exhibit good adhesion between the metal member and the resin film or plate. Similarly, lead frames constructed with at least two metal members, having a portion of the surface provided with an anodic oxide film of copper or a copper alloy, and in which these metal members are joined together through this anodic oxide film exhibit good adhesion between the metal members.
Abstract: According to this invention, an optical semiconductor device includes a flat metal plate, a glass member, a plurality of lead wires, an optical semiconductor element, and a cap member. The flat metal plate has a through hole in a direction of a thickness of the flat metal plate. The glass member is buried in the through hole of the flat metal plate. The plurality of lead wires are hermetically insulated and fixed in the flat metal plate through the glass member in the through hole. The optical semiconductor element is electrically connected to the lead wires. The cap member is fixed to the flat metal plate for housing the optical semiconductor element therein.
Abstract: Disclosed is a refractory covercoat composition useful in making two-sided circuitries. The refractory composition contains glass frit, and an inorganic binder including at least one selected from the group consisting of ZrO.sub.2, Al.sub.2 O.sub.3, SiO.sub.2, BaO, CaO, MgO and La.sub.2 O.sub.3. The refractory covercoat has an elevated softening point so that the covercoat protects a printed conductor circuit from damage due to contact with a firing furnace conveyor belt.
Abstract: A low-melting point glass sealed semiconductor device comprises a pair of ceramic substrates, each of which is shaped like an arch. The ceramic substrates are overlaid with each other, in such a manner as to define a space between them. Through this space, a gas generated from a thermosetting mounting agent used for adhesion is guided to the outside of the semiconductor device.