Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Abstract: A semiconductor laser element includes a substrate having a first main surface and a second main surface; a semiconductor layered body including an active layer, the semiconductor layered body being disposed on the first main surface; and a plurality of sub-patterns that, when combined, form an integrated pattern that allows reading of predetermined information, the plurality of sub-patterns being disposed on either one or both a first main surface side and a second main surface side of the substrate.

Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.

Abstract: A method for detecting an overlay error includes: forming a first overlay key including a plurality of spaced apart first target patterns having a first pitch on a first layer of a substrate; forming a second overlay key including a plurality of spaced apart second target patterns having a second pitch different than the first pitch on a second layer of the substrate below the first layer; irradiating the first layer and the second layer with incident light having a first wavelength; obtaining a phase pattern of light reflected from the first layer and the second layer; calculating a position of a peak point or a valley point of the phase pattern of the reflected light; and detecting an overlay error of the first layer and the second layer using the position of the peak point or the valley point of the phase pattern.

Abstract: An exposure method includes exposing a substrate to form a first pattern on a first layer, measuring a first alignment value of the first pattern, generating first correction data by using the first alignment value, storing the first correction data and exposing the substrate to form a second pattern on a second layer disposed on the first layer by using the first correction data.

Abstract: Passive dampers (e.g., a viscoelastic material such as a silicon gel) may be applied at one or more locations within an actuator module between a moving component (an optics assembly) and a fixed component (e.g., a cover attached to a base). The passive dampers act to passively dampen the motion of the optics assembly on the XY plane within the actuator module during optical image stabilization (OIS) of the optics assembly when subjected to external excitation or disturbance, and may also provide Z (optical) axis damping and impact protection. Process control and automation manufacturing and assembly methods for an OIS voice coil motor (VCM) actuator module including passive dampers are described, as well as design elements that provide for the integrity and reliability of the passive dampers over the life cycle of the actuator module.

Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

Abstract: The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.

Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.

Abstract: Disclosed is a thin-film transistor substrate including: a substrate; a thin-film transistor formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; an identification (ID) mark formed on the substrate; and a metal layer contacting an upper surface of the ID mark.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: Dies having alignment marks and methods of forming the same are provided. A method includes forming a device on a substrate. A plurality of contact pads is formed over the substrate and the device. Simultaneously with forming the plurality of contact pads, one or more alignment marks are formed over the substrate and the device.

Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

Abstract: Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents. The coated semiconductor substrate is heated to generate an acid in the trimming composition from the thermal acid generator, thereby causing a change in polarity of the matrix polymer in a surface region of the photoresist pattern. The photoresist pattern is contacted with a developing solution to remove the surface region of the photoresist pattern. The methods find particular applicability in the formation of very fine lithographic features in the manufacture of semiconductor devices.

Abstract: A mask for deposition includes a mask main body extended in a first direction and having a first thickness, and including ends opposite to each other in the first direction and supported by a frame while a tensile force is applied to the mask in the first direction; and a plurality of active patterns separated from each other in the first direction in a center area of the mask main body, and having a second thickness less than the first thickness.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is forced by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.

Abstract: A plurality of overlay errors in a structure is determined using a target that includes a plurality of diffraction based overlay pads. Each diffraction based overlay pad has the same number of periodic patterns as the structure under test. Additionally, each diffraction based overlay pad includes a programmed shift between each pair of periodic patterns. The pads are illuminated and the resulting light is detected and used to simultaneously determine the plurality of overlay errors in the structure based on the programmed shifts. The overlay errors may be determined using a subset of elements of the Mueller matrix or by using the resulting spectra from the pads.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?2 degrees to about 2 degrees towards (000-1) and less than about 0.5 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. A first cleaved c-face facet is provided on one end of the laser stripe region, and a second cleaved c-face facet is provided on the other end of the laser stripe region.

Abstract: A method of forming a silicon oxide film includes forming a silicon film on a base, the base being a surface to be processed of an object to be processed, and forming a silicon oxide film on the base by oxidizing the silicon film. Between the forming a silicon film and the forming a silicon oxide film, exposing the object to be processed having the silicon film formed thereon to an atmosphere containing at least an oxidizing component is performed.

Abstract: A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer.

Abstract: A loader module of a substrate processing system includes a transportation arm configured to move towards a wafer accommodated in a carrier and receive the wafer, and a control unit configured to confirm a delivery position of the wafer based on an upward movement amount of an end effector of the transportation arm, and a contact sound generated when the end effector comes in contact with the wafer. The control unit confirms the delivery position of the wafer based on an average height of the end effector when the contact sound of each pad of the end effector comes in contact with the wafer to generate a contact sound a plurality of times.

Abstract: An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Abstract: In a method of manufacturing a liquid crystal display device, a process for forming a first substrate includes the steps; forming a first wiring electrically connected with a switching element and extending in a first direction, forming an insulating film covering the first wiring, painting an electrically conductive film including electrically conductive material on the insulating film, and forming a second wiring electrically connected with the switching element extending in a second direction orthogonally crossing the first direction, and a pixel electrode electrically connected with the switching element apart from the second wiring by patterning the electrically conductive film. A second substrate is formed by forming a main common electrode extending in the second direction. A liquid crystal display panel is manufactured by holding liquid crystal material between the first substrate and the second substrate while the main common electrode faces the second wiring.

Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

Abstract: An organic light-emitting diode (OLED) display apparatus including a substrate, an insulation layer on the substrate, and an align mark formed of an insulation material, wherein an upper surface of the insulation layer contacts a lower surface of the align mark.

Abstract: A semiconductor device may include an enclosure structure. The semiconductor device may further include a getter for absorb gas molecules. The getter may be positioned (and enclosed) inside the enclosure structure and may overlap a first portion of a surface of the enclosure structure. The semiconductor device may further include an inductor. The inductor may be positioned (and enclosed) inside the enclosure structure and may overlap a second portion of the surface of the enclosure structure without overlapping the getter in a direction perpendicular to the first surface of the enclosure structure.

Abstract: A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die.

Abstract: A method is provided for fabricating a semiconductor substrate by forming a porous semiconductor layer conformally on a semiconductor template and then forming a semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the semiconductor substrate is formed on the semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the semiconductor substrate and is positioned between the inner trench and the edge of the semiconductor substrate. The semiconductor substrate is then released from the semiconductor template.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Abstract: Alignment of layers during manufacture of a multi-layer sample is controlled by applying optical measurements to a measurement site in the sample. The measurement site includes two diffractive structures located one above the other in two different layers, respectively. The optical measurements include at least two measurements with different polarization states of incident light, each measurement including illuminating the measurement site so as to illuminate one of the diffractive structures through the other. The diffraction properties of the measurement site are indicative of a lateral shift between the diffractive structures. The diffraction properties detected are analyzed for the different polarization states of the incident light to determine an existing lateral shift between the layers.

Abstract: An imprint apparatus that molds an imprint material on a substrate using a mold, and forms a pattern on the substrate, the imprint apparatus includes a mold holding unit configured to hold the mold, which includes a surface including a pattern area, a substrate holding unit configured to hold the substrate, a first acquisition unit configured to acquire information concerning a difference in shape between the pattern area and a shot already formed on the substrate, and a control unit configured to control at least one of the mold holding unit and the substrate holding unit to adjust a spacing between the mold and the substrate, based on the information concerning the difference in shape acquired by the first acquisition unit, in a state where the pattern area and the imprint material are in contact with each other.

Abstract: A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).

Abstract: A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole of a component and cannot be recognized by an image recognition apparatus. The metal film can be recognized by the image recognition apparatus. By forming a TiN film serving as a reflection prevention film on an end of the metal film, portions that can easily scatter light and a portion that cannot easily reflect light are adjacent in an alignment marker. A passivation film is formed on the interlayer insulating film and the TiN film. Recessed portions disposed in the metal film are exposed to a second opening portion formed in the passivation film and the TiN film.

Abstract: A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents. The coated semiconductor substrate is heated to generate an acid in the trimming composition from the thermal acid generator, thereby causing a change in polarity of the matrix polymer in a surface region of the photoresist pattern. The photoresist pattern is contacted with a developing solution to remove the surface region of the photoresist pattern. The methods find particular applicability in the formation of very fine lithographic features in the manufacture of semiconductor devices.

Abstract: Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.

Abstract: The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.

Abstract: A solid state imaging device includes a semiconductor substrate having an element isolating layer and a plurality of photoelectric conversion elements each formed in a respective one of a plurality of pixel regions that are isolated from each other by the element isolating layer, an interlayer dielectric layer having wires formed on a first surface of the semiconductor substrate, and a color filter layer having pigmented films of a plurality of colors, formed on a second surface of the semiconductor substrate and in the pixel regions. The element isolating layer has a part projecting from the second surface, and at least part of the pigmented films is formed in a space defined by the second surface and the projecting part of the element isolating layer.

Abstract: A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.

Abstract: A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.