Abstract: Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.

Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Abstract: A solid-state image pickup device includes: a silicon layer; a pixel portion formed in the silicon layer for processing and outputting signal charges obtained by carrying out photoelectric conversion for incident lights; an alignment mark formed in a periphery of the pixel portion and in the silicon layer; and a contact portion through which a first electrode within a wiring layer formed on a first surface of the silicon layer, and a second electrode formed on a second surface opposite to the first surface of the silicon layer through an insulating film are connected, wherein the alignment mark and the contact portion are formed from conductive layers made of the same conductive material and formed within respective holes each extending completely through the silicon layer through respective insulating layers made of the same material.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.

Abstract: A circuit layout structure includes a wafer having at least a cell region and a scribe line region defined thereon, a metal pattern formed in a first insulating layer in the scribe line region, a second insulating layer and a hard mask layer formed on the metal pattern and the first insulating layer, and at least a dummy pattern formed in the second insulating layer and the hard mask layer in the scribe line region. The dummy pattern has a transmission rate between 0% and 1%.

Abstract: A dicing die-bonding film and a method of forming a groove in a dicing die-bonding film, the film including a base film; a pressure-sensitive adhesive layer stacked on the base film; and a bonding layer stacked on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer includes a first region overlapping with the bonding layer, and a second region not overlapping with the bonding layer, the second region including a third region adjacent to the first region, and a fourth region adjacent to the third region and having a groove formed therein.

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.

Abstract: A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The dummy features have dimensions below a minimum resolution of an alignment detection tool. A minimum distance separating the overlay mark from its closest dummy feature is correlated to a semiconductor fabrication technology generation under which the overlay mark is formed.

Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: The invention provides a structure for critical dimension and overlay measurement including a measuring unit, a first measurement pattern for measuring overlay and a second measurement pattern for measuring linewidth, line density and/or line semi-density. The first target pattern includes an outer bar structure disposed on a first layer and an inner bar structure disposed on a second layer; the outer bar structure and/or the inner bar structure has a same shared pattern structure with the second target pattern. The pattern structure includes four bars with the same shape positioned orthogonally and closely to each other, and at least two orthogonally positioned bars include N equally spaced rectangular lines of the same width, wherein, N is an odd number; the N rectangular lines include one central rectangular line and N?1 auxiliary rectangular lines.

Abstract: A misalignment detection device comprising a first substrate, at least one integrated circuit, a second substrate, a third substrate, and at least one detection unit. The at least one integrated is disposed on the first substrate in a first pressing region. The third substrate is disposed on the first substrate in a second pressing region and on the second substrate on the second substrate in a third pressing region. The at least one detection unit outputs a fault signal in response to a positioning shift occurring in at least one of the first, second, and third pressing regions.

Abstract: An embodiment integrated circuit includes a first device supporting a first back end of line layer, the first back end of line layer including a first alignment marker, and a second device including a spin-on glass via and supporting a second back end of line layer, the second back end of line layer including a second alignment marker, the spin-on glass via permitting the second alignment marker to be aligned with the first alignment marker using ultraviolet light.

Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.

Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.

Abstract: A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire.

Abstract: A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern.

Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.

Abstract: A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

Abstract: Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided.

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract: A method of manufacturing a liquid crystal panel according to the present invention includes the steps of providing a marking pad including a marking region formed of a stack constituted only of a metal film serving as a lower layer and an ITO film serving as an upper layer on a main surface of a glass substrate, bonding a glass substrate to the glass substrate so as to be opposed to the main surface of the marking region in the marking pad at a distance therefrom, and providing marking by providing a through hole in the marking region in the marking pad by irradiating the marking region in the marking pad with laser beams through the glass substrate. Thus, the marking pad provided on the glass substrate for the liquid crystal panel can be provided with marking of high definition even though laser beams are emitted through another glass substrate for a liquid crystal panel paired with the glass substrate for the liquid crystal panel.

Abstract: According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers.

Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: In various embodiments, an assembly having a microstructure is provided, the device includes a cylindrical capture receptacle associated with a substrate, the capture receptacle comprising of a material having an expansion coefficient and comprising alignment structures having alignment projections extending inward from a periphery of the cylindrical capture receptacle. In one embodiment, the projections include a large width alignment projection and plurality of small width alignment projections. A plurality of medium width alignment projections also may be provided. A cylindrical key is associated with the microstructure and has a smaller circumference than the cylindrical capture receptacle and is comprised of a material having an expansion coefficient greater than the expansion coefficient of the cylindrical capture receptacle. The cylindrical key includes alignment receptacles spaced about a periphery of the cylindrical base to receive corresponding alignment projections.

Abstract: A bonding inspection structure is provided. The bonding inspection structure includes at least a elastic bump located on a substrate. At least an opening is formed in the top portion of the elastic bump. An inspection area of the top portion of the elastic bump is larger than an area of the opening.

Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.

Abstract: A substrate comprises a first mark and a second mark. The first mark comprises a first pattern with at least one mark feature formed by a first material and at least one further region formed by a second material. The first and second materials have different material characteristics with respect to a chemical-mechanical polishing process such that a step height in a direction substantially perpendicular to the surface of the substrate may be created by applying the chemical-mechanical polishing process. The second mark can be provided with a second step height by applying the chemical-mechanical polishing process. The second step height is substantially different from the first step height.

Abstract: An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements.

Abstract: The present invention discloses a method for cutting a substrate. The method includes the steps of 1) creating a etching groove in the first surface of the first sheet and the third surface of the second sheet; 2) laminating the first and second sheets with the etching grooves aligned with each other; and 3) using a cutter to cut through the second surface of first sheet and the fourth surface of the second sheet along a preset set cutting line such that a crack extending vertically to the etching grooves so as to sever the first and second sheets. The present invention further discloses a substrate. By way of the foregoing, the taper and gradient along the cutting edge can be reduced.

Abstract: An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.

Abstract: A loadport for handling film frames is disclosed. The loadport is modular and substantially compatible with applicable standards regarding modular equipment. In particular, the load port is substantially interchangeable with loadports not adapted for handling film frames. The loadport has a compact shuttle for moving film frames and flexible alignment mechanisms for aligning film frames and cassettes of different configurations.

Abstract: A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.

Abstract: Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided.

Abstract: In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described.

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract: An alignment mark may include: an elongate pattern having first and second end portions and a central portion located between the first and second end portions, wherein at least one of the first and second end portions has a larger width than the central portion.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. Techniques for imaging targets with flexible symmetry characteristics and analyzing the acquired images to determine overlay or alignment error are disclosed.