Abstract: An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.

Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

Abstract: The invention relates to a solar-cell marking method comprising the steps of: providing a substrate with a substrate surface for producing a solar cell (1) that comprises an active zone (5); and producing at least one indentation (21, 31) in the substrate surface with the use of laser irradiation, wherein the at least one indentation (21, 31) forms a marking (2, 3) for marking the solar cell (1), and producing the indentation (21, 31) is carried out prior to carrying out a solar-cell manufacturing process or during carrying out a solar-cell manufacturing process. According to the invention the substrate is designed as a semiconductor wafer with a wafer surface, and the marking (2, 3) is positioned on the wafer surface such that the marking (2, 3) is in the active zone (5) of the solar cell (1) formed by the semiconductor wafer.

Abstract: There is provided a light emitting diode package, including a package body including a recess portion having a housing space and a lead frame mounted on the recess portion to be exposed; a light emitting diode chip mounted to be electrically connected to the lead frame; and a position indicator formed on the lead frame and guiding the mounting position of the light emitting diode chip.

Abstract: An overlay mark for checking alignment accuracy between a former layer and a later layer on a wafer is described, including a former pattern as a part of the former layer, and a later pattern as a part of a patterned photoresist layer defining the later layer. The former pattern has two parallel opposite edges each forming a sharp angle ? with the x-axis of the wafer. The later pattern also has two parallel opposite edges each forming the sharp angle ? with the x-axis of the wafer.

Abstract: A method and structure for mechanical self-alignment of semiconductor device features, for example multi-chip module features. Alignment of the features can be performed using mechanical alignment grooves within a layer of a first device and mechanical alignment pedestals of a second device. The alignment accuracy is limited by the patterning resolution of the semiconductor processing, which is in sub-micron scale. Flip-chip bonding can be used as the bonding process between chips to increase the alignment precision.

Abstract: Provided is a transport method comprising judging whether there is a possibility that misalignment greater than or equal to a threshold value occurs between substrates to be layered that are held by a pair of substrate holders aligned and stacked by an aligning section, the misalignment occurring when the pair of substrate holders is transported from the aligning section to a pressure applying section; and if the judgment indicates that there is the possibility of misalignment, transporting the pair of substrate holders to a region other than the pressure applying section. Whether there is the possibility of misalignment may be judged based on at least one of an acceleration of the substrate holders, an acceleration of a transporting section that transports the substrate holders, relative positions of the substrate holders, or relative positions of the transporting section and one of the pair of substrate holders.

Abstract: A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench, that is formed on the via hole and communicates with the via hole, are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally fill the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening, that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view, are formed, and in the groove portion and the opening, a conductor is provided so as to integrally fill the groove portion and the opening.

Abstract: A semiconductor device includes a die pad, the die pad including a first surface and a second surface, a first chip arranged on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged on the first surface, a plurality of first recesses formed on the first surface, a plurality of second recesses formed on the first surface, the plurality of second recesses being different from the first plurality of recesses in at least one of size and geometry, a wire, a resin, and a lead, one end of the lead being connected to another end of the wire and a part the lead being encapsulated by the resin. The plurality of first recesses includes a third recess and a fourth recess, and the first chip is arranged in a first area.

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

Abstract: A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device.

Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

Abstract: An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements.

Abstract: In one embodiment, a semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of first structures that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures and a plurality of second structures that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures. The first rotation angles differ from the second rotation angles, and first structures and second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.

Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques.

Abstract: There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion.

Abstract: A method of manufacturing a super-junction semiconductor device facilitates suppressing the shape change caused in the alignment mark in the upper epitaxial layer transferred from the alignment mark in the lower epitaxial layer to be small enough to detect the transferred alignment mark with a few additional steps, even if the epitaxial layer growth rate is high. Alignment mark groups, each formed of trenches including parallel linear planar patterns and used in any of the multiple epitaxial layer growth cycles, are formed collectively on a scribe line between semiconductor chip sections; and the mesa region width between the trenches in each alignment mark group indicated by the distance between the single-headed arrows, facing opposite to each other and drawn in alignment mark groups is set to be one fourth of the designed total epitaxial layer thickness at the end of each epitaxial layer growth cycle or longer.

Abstract: An overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure including a set of two or more pattern elements, wherein the target structures are configured to provide metrology information pertaining to different pitches, different coverage ratios, and linearity. Pattern elements may be separated from adjacent pattern elements by non-uniform distance; pattern elements may have non-uniform width; or pattern elements may be designed to demonstrate a specific offset as compared to pattern elements in a different layer.

Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe.

Abstract: A misalignment detection device comprising a substrate, at least one integrated circuit (IC), and at least one detection unit is disclosed. The substrate comprises a first positioning pad and a second positioning pad adjacent to the first positioning pad. The integrated circuit is disposed on the substrate and comprises a first positioning bump and a second positioning bump adjacent to the first positioning bump. The first and second positioning bumps substantially correspond to the first and second positioning pads, respectively. The at least one detection unit is electrically coupled to the substrate, wherein the detection unit outputs a fault signal in response to a positioning shift occurring between the first and second positioning pads and the first and second positioning bumps.

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern.

Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.

Abstract: A circuit includes a plurality of integrated circuits or dies having corresponding circuits, the plurality of integrated circuits or dies include a first plurality of integrated circuits or dies having corresponding millimeter wave interfaces and a second plurality of integrated circuits or dies having corresponding inductive interfaces. The first plurality of integrated circuits or dies communicate first signals therebetween via the corresponding millimeter wave interfaces and the second plurality of integrated circuits or dies communicate second signals therebetween via the corresponding inductive interfaces.

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.

Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.

Abstract: A TFT array substrate including a substrate, a plurality of pixel structures and a plurality of cutting marks is provided. The substrate has a device region and a cutting mark region. The pixel structures are disposed in the device region and each pixel structure includes a TFT, a pixel electrode and a passivation layer covering the TFT. The cutting marks are within the cutting mark region, disposed at two sides of a predetermined cutting position, and are arranged as a row or column perpendicular to a predetermined cutting direction. In particular, the cutting marks are constituted of at least two colors, at least two shapes, at least one color and at least one shape, or a combination thereof.

Abstract: A thin film transistor (TFT) array substrate includes a substrate having a plurality of normal alignment regions, a plurality of abnormal alignment regions, and a device region defined thereon, a plurality of scan lines, a plurality of data lines, a plurality of storage electrode lines, and a plurality of switch devices positioned in the device region, a plurality of alignment structures positioned in the abnormal alignment regions, and an alignment layer formed on the substrate and the alignment structures. The alignment layer further includes a plurality of first alignment slits covering the alignment structures in the abnormal alignment regions and a plurality of second alignment slits in the normal alignment regions. A depth and a width of the second alignment slits are identical to a depth and a width of the first alignment slits.

Abstract: Semiconductor wafer alignment markers and associated systems and methods are disclosed. A wafer in accordance with a particular embodiment includes a wafer substrate having an alignment marker that includes a first structure and a second structure, each having a pitch, with first features and second features positioned within the pitch. The first features are positioned to generate first phase portions of an interference pattern, with at least one of the first features having a width different than another of the first features in the pitch, and with the second features positioned to generate second phase portions of the interference pattern, with the second phase portions having a second phase opposite the first phase, and with at least one of the second features having a width different than that of another of the second features in the pitch. The pitch for the first structure is different than the pitch for the second structure.

Abstract: A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: The present invention consists of a method for imparting asymmetry to a truncated annular wafer by either rounding one corner of the orientation flat, or rounding one corner of a notch. This novel method of rounding corners impart a visual and/or tactile asymmetry which can be utilized by a person in order to differentiate between the two different sides of the wafer. This inventive wafer design and method for making an asymmetric wafer is especially useful in the field of semiconductor technology and may be used on sapphire crystal wafers or any other class of wafer.

Abstract: Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases.

Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Abstract: A method and apparatus is presented for obtaining high resolution positional feedback from motion stages 52 in indexing systems 10 without incurring the costs associated with providing high resolution positional feedback from the entire range of motion by combining low resolution/low cost feedback devices 72 with high resolution/high cost feedback devices 74, 76, 78, 80, 82, 84, 86, 88.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.

Abstract: An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.

Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

Abstract: A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.