Abstract: A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.

Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.

Abstract: Generally, the subject matter disclosed herein relates to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor. In one example, the method includes forming a layer of insulating material, forming a capacitor opening in the layer of insulating material, forming a sealing liner on the sidewalls of the capacitor opening and forming a first metal layer in the capacitor opening and on the sealing liner by performing a process using a precursor having a minimum particle size, wherein the sealing liner is made of a material having an opening size that is less than the minimum particle size of the precursor.

Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract: In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.

Abstract: A method of manufacturing a semiconductor memory device includes forming a first capacitor using a metal oxide semiconductor (MOS) transistor, forming a second capacitor being a pillar type corresponding to a cell capacitor formed in a cell region, and forming a third capacitor over the first and the second capacitors.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.

Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

Abstract: A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film.

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

Abstract: A method of manufacturing a semiconductor device including forming on a substrate an insulating interlayer through which a capacitor contact is interposed; forming on the insulating interlayer a first upper electrode having an opening through which the capacitor contact is exposed; forming a first dielectric layer pattern on a lateral wall of the opening; forming a lower electrode on the first dielectric layer pattern formed in the opening and the capacitor contact; forming a second dielectric layer pattern on the lower electrode formed in the opening and the first dielectric layer pattern; and forming on the second dielectric layer pattern a second upper electrode so as to fill the opening and to contact the first upper electrode. The semiconductor device may prevent a lower electrode of a capacitor from collapsing.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.

Abstract: A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer.

Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

Abstract: A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

Abstract: A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

Abstract: A packaging substrate includes: a substrate having a core layer, a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; a first capacitor disposed in the cavity; a bonding layer formed on the first capacitor in the cavity of the substrate; a second capacitor disposed on the bonding layer so as to be received in the cavity; and a dielectric layer formed on the substrate and in the cavity for covering the first and second capacitors. By stacking the first and second capacitors in the cavity through the bonding layer, the single core layer is embedded with two layers of the capacitors to thereby meet the multi-function requirement.

Abstract: Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

Abstract: A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

Abstract: A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer.

Abstract: The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

Abstract: A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.

Abstract: A process for making a dielectric material where a precursor polymer selected from poly(phenylene vinylene)polyacetylene, poly(p-phenylene), poly(thienylene vinylene), poly(1,4-naphthylene vinylene), and poly(p-pyridine vinylene) is energized said by exposure by radiation or increase in temperature to a level sufficient to eliminate said leaving groups contained within the precursor polymer, thereby transforming the dielectric material into a conductive polymer. The leaving group in the precursor polymer can be a chloride, a bromide, an iodide, a fluoride, an ester, an xanthate, a nitrile, an amine, a nitro group, a carbonate, a dithiocarbamate, a sulfonium group, an oxonium group, an iodonium group, a pyridinium group, an ammonium group, a borate group, a borane group, a sulphinyl group, or a sulfonyl group.

Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.

Abstract: Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.

Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Abstract: The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (Toff).

Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening.

Abstract: According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.