Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.

Abstract: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor device manufacturing method includes loading a substrate to a processing chamber, a gate insulating film or a capacitor insulating film being formed on a surface of the substrate; forming an electrode, which includes a conductive oxide film and to which an additive that modulates a work function of the conductive oxide film is added, on the substrate; and unloading the substrate, on which the electrode is formed, from the processing chamber.

Abstract: A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions.

Abstract: A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.

Abstract: A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer.

Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.

Abstract: A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilsicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack an don exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract: Methods for fabricating a capacitor are provided. In the methods, a dielectric may be formed on a metal (e.g. nickel) substrate, and a copper electrode is formed thereon, followed by the thinning of the metal substrate from its non-coated face, and subsequently forming a copper electrode on the thinned, non-coated face of the substrate.

Abstract: An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.

Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

Abstract: Provided are a capacitive transducer, and methods of manufacturing and operating the same. The capacitive transducer includes: a monolithic substrate comprising a first doping region, a second doping region that is opposite in conductivity to the first doping region, and a vibrating portion; and an empty space that is disposed between the first doping region and the vibrating portion. The vibrating portion includes a plurality of through-holes, and a material film for sealing the plurality of through-holes is disposed on the vibrating portion.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a doped material formed from a first dopant in concert with a second dopant wherein the second dopant has a different physical size from the first dopant and the presence of the second dopant influences the solubility of the first dopant in the dielectric material.

Abstract: A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

Abstract: The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.

Abstract: A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.

Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening having open end shape in which open end length is elongated compared with an opening having linear open end shape.

Abstract: A device comprises a substrate having at least one active region, an insulating layer above the substrate, and an electrode in a gate electrode layer above the insulating layer, forming a metal-oxide-semiconductor (MOS) capacitor. A first contact layer is provided on the electrode, having an elongated first pattern extending in a first direction parallel to the electrode. A contact structure contacts the substrate. The contact structure has an elongated second pattern extending parallel to the first pattern. A dielectric material is provided between the first and second patterns, so that the first and second patterns and dielectric material form a side-wall capacitor connected in parallel to the MOS capacitor.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract: A capacitor insulating film may include, but is not limited to, strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of (200) crystal face of the capacitor insulating film to a spectrum intensity of (111) crystal face of the capacitor insulating film in the range of 1.0 to 2.3. Each of the spectrum intensities of (200) crystal face and (111) crystal face is measured by an X-ray diffraction method.

Abstract: Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 K?˜30 K?) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

Abstract: A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.

Abstract: Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode.

Abstract: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.

Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove.

Abstract: A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor.

Abstract: A method of forming a semiconductor device includes the following processes. A dummy insulating film is formed over a semiconductor substrate by using a source material that is free of carbon as an essential component. A hole that penetrates the dummy insulating film is formed. A conductive film is formed, which covers at least a side wall of the hole of the dummy insulating film. The dummy insulating film is removed to expose an outer surface of the conductive film.

Abstract: A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one deep trench is formed on the backside of the semiconductor substrate in the bottom semiconductor layer and at least one dielectric layer thereupon. A node dielectric and a conductive inner electrode are formed in each of the at least one deep trench. Substrate contact vias abutting the bottom semiconductor layer are also formed in the at least one dielectric layer. Conductive wiring structures on the backside of the semiconductor substrate provide lateral connection between the through substrate vias and the at least one conductive inner electrode and the substrate contact vias.

Abstract: A pyroelectric detector includes a pyroelectric detection element, a support member and a support part. The pyroelectric detection element has a capacitor including a first electrode, a second electrode, and a pyroelectric body. The support member includes first and second sides with the pyroelectric detection element being mounted on the first side and the second side facing a cavity. The support part, the support member, and the pyroelectric detection element are laminated in this order in a first direction with the cavity being formed between the support part and the support member. The support member has at least a first insulation layer on the first side contacting the first electrode, with the first insulation layer having a hydrogen content rate smaller than a hydrogen content rate of a second insulation layer positioned further in a second direction than the first insulation layer, the second direction being opposite the first direction.

Abstract: A pyroelectric detector includes a pyroelectric detection element mounted on a first side of a support member with a second side facing a cavity. The pyroelectric detection element has a capacitor including a first electrode, a pyroelectric body and a second electrode, and an interlayer insulation layer forming first and second contact holes passing respectively through to the first and second electrodes. First and second plugs are respectively embedded in the first and second contact holes, with first and second electrode wiring layers are respectively connected to the first and second plugs. A thermal conductivity of material of the second electrode wiring layer is lower than a thermal conductivity of material of a portion of the second electrode connected to the second plug.

Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.

Abstract: In an apparatus for manufacturing a ceramic thin film by employing a thermal CVD method, an internal jig, which is provided with a heat radiation material film on the surface, is provided at a position that faces a substrate (S) on which the film is to be formed. The thin film and a semiconductor device are manufactured using such apparatus.

Abstract: When producing ferroelectric memory devices on a wafer, a memory cell expected to provide the severest degradation of fatigue characteristics is selected from a chip region of the wafer in which the fatigue characteristics are expected to be the poorest, based on the knowledge acquired in advance with regard to the in-plane distribution of the fatigue characteristics on a wafer. The predetermined number of times of rewriting data is guaranteed by conducting fatigue test in the memory cell thus selected for all of the wafers such that, when the result of the fatigue test is good, the entire devices on the wafer are rendered good with regard to the fatigue characteristics.

Abstract: Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.