Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A method for scaling channel length in a semiconductor device is provided. The method includes increasing a pitch to reduce a development inspection critical dimension (DICD) for a plurality of polysilicon lines. The polysilicon lines are trimmed to provide a reduced-size channel length, based on the reduced DICD, for each polysilicon line. For a particular embodiment, the semiconductor device is fabricated using a photolithography tool having a wavelength of 248 nm, the pitch is about 800 nm, and the reduced-size channel length is about 0.11 ?m.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.

Abstract: A method of manufacturing a semiconductor device according to an embodiment includes processing a second film 14 formed on a semiconductor substrate to a pattern including a plurality of linear parts and end portions formed in an end of each of the linear parts, having a width wider than the linear parts, forming a first pattern 16 by slimming the pattern, forming a second pattern including a first opening 180 that traverses the end portion 141a of the first pattern 16, etching the second film 14 exposed in the first opening 180, and dividing the end portion 141a into a first end portion 142a close to the linear part 140a and a second end portion 143a apart from the linear part 140a.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.

Abstract: A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched.

Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Abstract: Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.

Abstract: An electronic component or display device of the present invention can be provided by using a following pattern formation method. On a substrate treated with a first etching with a first resist pattern as a first mask, a second resist pattern is transfer-printed on the first resist patterns so as to partially overlap with the first resist pattern and partially extended from the first resist pattern. And then a second etching is performed by using the first resist pattern and the second resist pattern as a second mask. The first resist pattern and the second resist pattern are used for forming wirings and/or terminals, and the extended portion of the second resist pattern is used to make the wirings to have a cross section of a stair-like edge shape.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract: A lead frame comprises on a same plane, a pad part including an LED chip mounting upper surface A on which at least an LED chip is to be mounted, and a lead part including an electric connection area C in which an electric connection with the LED chip is made. A relationship between an area S1 of the mounting upper surface of the pad part 2 and an area S2 of a radiating lower surface opposite to the mounting upper surface is represented by 0<S1<S2. Side surfaces of the pad part between the mounting upper surface and the radiating lower surface are provided with stepped parts or tapered parts which spread in a direction from the mounting upper surface toward the radiating lower surface and hold a resin-filled during molding.

Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behaviour is obtained that may be applicable in many fields.

Abstract: A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.

Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.

Abstract: A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nano

Abstract: A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.

Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

Abstract: A light emitting display device includes a first electrode formed at a light emitting region of a first substrate; a transparent oxide thin film of about 1 ? to about 200 ? in thickness formed on an entire surface of the first electrode at the light emitting region to substantially cover particle on the entire surface of the first electrode; an organic light emitting layer formed on an entire surface of the oxide thin film to emit a light; and a second electrode formed on an entire surface of the first substrate including the organic light emitting layer.

Abstract: A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

Abstract: Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ? the width of lines in the first pattern.

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.

Abstract: A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.

Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.

Abstract: A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask comprised of a series of lines is first provided. A spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask is then formed. The spacer mask also has interposed lines between the spacer lines. Finally, the sacrificial mask is removed to provide only the spacer mask. The spacer mask having interposed lines triples the frequency of the series of lines of the sacrificial mask.

Abstract: A method for applying a predetermined structure of a structural material to a semiconductor element. The method includes the following steps: A) partially covering a surface of the semiconductor element with a masking layer, B) applying a film of a structural material to the masking layer and to the surface of the semiconductor element in the zones that are devoid of the masking layer and C) removing the masking layer together with the structural material present on the masking layer. The method according to the invention provides that between process steps B and C, the film of structural material is partially removed in a process step B2.

Abstract: A system and method of manufacturing a semiconductor device lithographically and an article of manufacture involving a lithographic double patterning process having a dye added to either the first or second lithographic pattern are provided. The dye is used to detect the location of the first lithographic pattern and to directly align the second lithographic pattern to it. The day may be fluorescent, luminescent, absorbent, or reflective at a specified wavelength or a given wavelength band. The wavelength may correspond to the wavelength of an alignment beam. The dye allows for detection of the first lithographic pattern even when it is over coated with a radiation sensitive-layer (e.g., resist).

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract: Methods are described for forming an integrated circuit having multiple devices, such as transistors, with respective element lengths. The methods include a new CAD flow for producing masks used for exposing sidewall spacers which are to be etched to a smaller base width than other sidewall spacers and which in turn are used as an etch mask to form gate structures with smaller element lengths than those formed from the other sidewall spacers.

Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees with the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist.

Abstract: A method for forming a mask pattern for ion-implantation comprises: forming a gate line pattern over a semiconductor substrate; forming a coating layer on the surface of gate line pattern; performing a plasma treatment on the top portion of the gate line pattern; forming a photoresist layer over the resulting structure; and performing an exposure and a developing processes to form a photoresist pattern on the gate line pattern.

Abstract: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5)

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer; etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate; depositing a conductive film; and removing the photoresist layer; to form a pixel electrode on a portion of the drain electrode exposed by the etching of the passivation layer.

Abstract: A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.

Abstract: A transmissivity controlled film 12 (CrO or the like), a transmissivity reduced film 13 (Cr or the like), and a resist film 14, for instance, are sequentially formed on, e.g., a transparent substrate 11. A resist is removed from an area (an area C) where a light-transmission section is to be formed, and the transmissivity reduced film 13 and the transmissivity controlled film 12 are removed from the area, thereby forming a light-transmission section. Next, a resist is removed from an area (an area A) in which a graytone section is to be formed, thereby removing the transmissivity reduced film 13 from that area, to thereby form a graytone section. Thus, a graytone mask is manufactured.