Abstract: A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.

Abstract: Disclosed is a photosensitive resin composition showing excellent contrast performance after exposure to light. Also disclosed is a photosensitive resin laminate using the composition. The photosensitive resin composition comprises (a) 20 to 90% by mass of a binder having a carboxyl group, (b) 5 to 75% by mass of an addition-polymerizable monomer having at least one ethylenically unsaturated terminal group, (c) 0.01 to 30% by mass of a photopolymerization initiator, and (d) 0.01 to 10% by mass of a leuco dye, wherein a specific binder is contained as the binder (a) and a specific monomer is contained as the addition-polymerizable monomer (b).

Abstract: The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such that part of the photosensitive layer (R) covers at least part of the first layer (E1), exposing the photosensitive layer (R) to a light beam (L), the light beam (L) impinging on the lower surface of the substrate (S) under an oblique angle (?) of incidence, removing the exposed region of the photosensitive layer (R), depositing a second layer (E2) of an opaque material such that part of the second layer (E2) covers a remaining region of the photosensitive layer (R), and removing at least a part of the remaining region of the photosensitive layer (R).

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.

Abstract: A multi-chip lighting module is disclosed for maximizing luminous flux output and thermal management. In one embodiment, a multi-chip module device comprises a substantially thermally dissipative substrate with a dark insulating layer deposited on a surface of the substrate. A plurality of light emitting devices is also provided. An electrically conductive layer is applied to a surface of the substrate, with the conductive layer comprising a plurality of chip carrier parts each having a surface for carrying at least one of the light emitting devices. Each light emitting device has a first and a second electrical terminal. A reflective layer is also provided that at least partially covers the conductive layer.

Abstract: A test structure and a method for fabricating the same are disclosed. The test structure includes a plurality of sampling lines over a substrate located between a plurality of a first grounding lines and a plurality of a second grounding lines. The sampling lines are selectively electrically coupled to the first grounding line or the second grounding line and include at least one programmed defect. A double-patterning fabricating approach is utilized to produce such test structure which may be applied to a charged particle beam such as an electron-beam defect inspection system.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: The present invention provides: a liquid crystal display device capable of improving display qualities and yield, the liquid crystal display device having two or more domains in a pixel through an alignment treatment that has been provided for a substrate over several times; and a production method thereof.

Abstract: A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

Abstract: According to an aspect of the present invention, there is provided a method for evaluating a process model, the method including: acquiring, for each of given patterns, a dimensional difference amount between: a first pattern that is formed by actually applying a process onto a corresponding one of the given patterns; and a second pattern that is calculated by applying a process model modeling the process to the corresponding one of the given patterns; and evaluating the process model based on an evaluation index, the evaluation index being based on the number of the patterns at which the dimensional difference amount is equal to or less than a threshold value.

Abstract: A method of patterning a substrate using a dual-tone development process is described. The patterning method comprises forming a layer of radiation-sensitive material on a substrate, wherein the layer of radiation-sensitive material comprises a dual tone resist. Thereafter, the patterning method comprises performing one or more exposures of the layer of radiation-sensitive material to one or more patterns of radiation, wherein at least one of the one or more exposures comprises using a mask having a dual-tone mask pattern region configured for printing dual tone features and a half-tone mask pattern region configured for printing half-tone features. Furthermore, the half-tone mask pattern region is optimized for use with the dual tone resist.

Abstract: A front-surface-illuminated photovoltaic device, having a first semiconductor layer (180) with a back surface, a second semiconductor layer (130) with a front surface, the second layer (130) having the opposite doping type to the first layer (180) and deposited on the first layer (180); and at least one ohmic contact (160, 230) to each of the first (180) and second (130) semiconductor layers; and a process for making the photovoltaic device. The device may also have a barrier layer (190) for reducing diffusion of impurities from the first semiconductor layer (180) into the second semiconductor layer (130), a blocking layer (120), and a reflector layer (200). The device may have an array of first regions (115) in which the second layer (130) is of opposite doping type to that of the first layer (180) and forms p-n junctions (240) in these first regions (115), and second regions (300), each second region (300) containing the barrier layer (190) and the reflector layer (200).

Abstract: A thin film transistor array panel includes a substrate; a first gate line disposed on the substrate and including a gate electrode; a storage electrode disposed in a layer which is the same layer as a layer of the first gate line; a gate insulating layer disposed on the first gate line and the storage electrode; a semiconductor disposed on the gate insulating layer and including a channel portion; a data line disposed on the semiconductor and including a source electrode; a drain electrode disposed on the semiconductor and facing the source electrode; a passivation layer disposed on the gate insulating layer, the data line, and the drain electrode, the passivation layer including a contact hole which exposes a portion of the drain electrode; and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode through the contact hole, wherein the gate insulating layer and the passivation layer are interposed between the pixel electrode and the substrate except for a regio

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: A method for correcting a mask pattern to be formed on a photomask used in a lithographic step of a semiconductor device fabrication process. The method includes the steps of extracting an isolated pattern having an optically isolated portion from the mask pattern and providing, in an adjacent pattern extending parallel to the isolated portion of the isolated pattern and having a terminal end, an extended portion extending from the terminal end next to the isolated portion of the isolated pattern along a direction in which the isolated portion of the isolated pattern extends.

Abstract: A light emitting display device includes a first electrode formed at a light emitting region of a first substrate; a transparent oxide thin film of about 1 ? to about 200 ? in thickness formed on an entire surface of the first electrode at the light emitting region to substantially cover particle on the entire surface of the first electrode; an organic light emitting layer formed on an entire surface of the oxide thin film to emit a light; and a second electrode formed on an entire surface of the first substrate including the organic light emitting layer.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A damping apparatus that supports and dampens a stage apparatus that positions and drives a stage to a target position is provided herein. The damping apparatus including a support plate part, a support force generating means, and a first controlling means. The support plate part supports the stage apparatus. The support force generating means exerts a damping action by applying a support force to the support plate part in the vertical directions. The first controlling means uses the acceleration of the stage, which is derived from a target track, to the target position, to control the support force generated by the support force generating means so as to compensate for forces that both occur as a result of the acceleration of the stage and cause the support plate part to tilt. The present invention controls vibration and the tilt of a base plate with high precision.

Abstract: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate includes a substrate and a pixel array on the substrate. Each pixel has: a gate line and a gate electrode formed on the substrate; a gate insulating layer formed on the gate line and the gate electrode; a semiconductor layer formed on the gate insulating layer disposed on the gate electrode; an ohmic contact layer having two parts, which are disposed on two sides of the semiconductor layer respectively and are apart from one another; an isolation insulating dielectric layer covering the substrate and the gate insulating layer except a portion on which the semiconductor layer is formed; a pixel electrode formed on the isolation insulating dielectric layer and the ohmic contact layer over the semiconductor layer; a source/drain electrode formed on the pixel electrode over the ohmic contact layer, and a passivation layer at least covering the semiconductor layer.

Abstract: A light emitting device includes a light emitting layer made of semiconductor; an upper electrode including a bonding electrode capable of connecting a wire thereto and a thin-wire electrode surrounding the bonding electrode with a spacing and including a junction with the bonding electrode, and a current diffusion layer provided between the light emitting layer and the upper electrode and made of semiconductor, the current diffusion layer including a recess that is formed in a non-forming region of the upper electrode and capable of emitting light emitted from the light emitting layer.

Abstract: A method for manufacturing a solar cell includes providing a first conductivity type doped crystalline silicon wafer, depositing on one side a first intrinsic a-Si:H buffer layer, followed by a second conductivity type doped a-Si:H layer, turning over the wafer and depositing on the opposite side a surface passivating anti-reflection coating, applying a first mask having a grid opening on the second conductivity type doped a-Si:H covered surface of the wafer, dry etching to remove the second conductivity type doped a-Si:H layer not covered by the first mask, while maintaining the first mask in position: depositing a second intrinsic buffer layer of a-Si:H, depositing a first conductivity type doped a-Si:H layer.

Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the first film thickness, is formed on the stopper film. A first mask is formed by patterning the first mask material. An opening portion is formed by etching the stopper film using the first mask. The opening portion is filled with a second mask material. A second mask of the second mask material is formed by removing the stopper film. The insulation film is etched using the second mask.

Abstract: A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures.

Abstract: A large-size glass substrate, from which a photomask substrate is formed, is prepared by processing a large-size glass substrate stock by (1) a flattening removal quantity based on height data of the substrate stock in the vertical attitude plus a deformation-corrective removal quantity. The deformation-corrective removal quantity is calculated from (2) a deflection of the substrate stock by its own weight in the horizontal attitude, (3) a deformation of the photomask substrate caused by chucking in an exposure apparatus, and (4) an accuracy distortion of a platen for supporting a mother glass.

Abstract: A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit.

Abstract: The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact holes of a first dielectric layer is first provided. An etch-stop layer and a hard mask pattern are formed over the first dielectric layer and the contact plugs. The etch-stop layer is patterned along the hard mask pattern. The exposed first dielectric layer and the contact plugs are etched to thereby form trenches in the first dielectric layer over the contact plugs. A metal layer is formed to gap-fill the trenches. A polishing process is performed to expose the etch-stop layer.

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract: An exposure apparatus for transferring patterns on a phase shift mask into a wafer according to the present invention comprises a light source, a polarized light illuminator that selectively passes through a TM mode polarized light of light from the light source to cause it to be incident onto the phase shift mask, a polarization mode translator that translates the TM mode polarized light passing through the phase shift mask into TE mode polarized light, and a lens system irradiating the TE mode polarized light from the polarization mode translator on the wafer.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

Abstract: A manufacturing method of an electrophoretic display device including a pair of substrates with an electrophoretic element therebetween, the electrophoretic element containing electrophoretic particles therein, and a display portion with a plurality of pixels arranged therein, each pixel including a selection transistor and a latch circuit connected to the selection transistor, the manufacturing method including a semiconductor portion forming process for forming a first semiconductor portion which constitutes the selection transistor and a second semiconductor portion composed of a plurality of transistors which constitutes a feedback inverter of the latch circuit so that the first semiconductor portion and the second semiconductor portion are placed in a straight line form extending in a direction of arrangement of the pixels, and an irradiating process for irradiating the first and second semiconductor portions with pulse-form light along the arrangement of the straight line form.

Abstract: A micro-optic device including a complicate structure and a movable mirror is made to be manufactured in a reduced length of time. A silicon substrate and a single crystal silicon device layer with an intermediate layer of silicon dioxide interposed therebetween defines a substrate on which a layer of mask material is formed and is patterned to form a mask having the same pattern as the configuration of the intended optical device as viewed in plan view. A surface which is to be constricted as a mirror surface is chosen to be in a plane of the silicon crystal. Using the mask, the device layer is vertically etched by a reactive ion dry etching until the intermediate layer is exposed. Subsequently, using KOH solution, a wet etching which is anisotropic to the crystallographic orientation is performed with an etching rate which is on the order of 0.1 ?m/min for a time interval on the order of ten minutes is performed to convert the sidewall surface of the mirror into a smooth crystallographic surface.

Abstract: A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.

Abstract: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.

Abstract: The present invention relates to a method of forming patterns of a semiconductor device. In an aspect of the present invention, the method may include providing a semiconductor substrate, including a first area in which patterns are formed at a first interval and a second area formed wider than the first interval, forming an etch mask layer formed over the semiconductor substrate, forming photoresist patterns formed over the etch mask layer, wherein an auxiliary pattern is formed at an outermost area of the second area, forming first etch mask patterns by patterning the etch mask layer using the photoresist patterns and the auxiliary pattern, forming an auxiliary layer on the entire surface including the first etch mask patterns, forming a second etch mask pattern in concave portions of the auxiliary layer, and removing the auxiliary layer that is exposed.

Abstract: A light emitting apparatus includes a support having circuitry disposed thereon, at least one light emitting diode (LED) chip mounted on the support and in electrical communication with the circuitry and a reflective layer on the support adjacent the at least one chip.

Abstract: In a method for manufacturing an image sensor, an interlayer insulating layer including a metal line is formed on a semiconductor substrate. A lower electrode layer is formed on the metal line such that the lower electrode is connected with the metal line. A photoresist pattern corresponding to the metal line is formed on the lower electrode layer. The lower electrode layer is etched using the photoresist pattern to form a lower electrode connected with the metal line. The photoresist pattern is stripped using a solvent containing fluorine.

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.

Abstract: A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.

Abstract: A light emitting diode comprises a substrate having a first surface and a second surface, a light emitting epitaxy structure placed on the first surface of the substrate, and a compound reflection layer placed on the second surface of the substrate. The second surface of the substrate further has a protection structure.

Abstract: A liquid crystal display panel includes: a thin film transistor array substrate having a gate line and a data line provided on the substrate; a gate insulating film between the gate line and the data line; a thin film transistor having a source electrode, a drain electrode and a gate electrode; a pixel electrode; a protective film for protecting the thin film transistor; a plurality of pads; a transparent electrode pattern formed on the data line, source electrode and drain electrode; and a color filter array substrate joined to the thin film transistor array substrate so that the color filter substrate does not overlap the pad area of the thin film transistor array substrate, wherein at least one of the gate insulating film and protective film in the pad area is etched using the color filter array substrate as a mask to expose at least one of the plurality of pads.

Abstract: Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a multi-tone mask, a photoresist layer is formed, which has a tapered shape in which the area of a cross section is reduced gradually in a direction away from one mother glass substrate. At the time of forming one wiring, one photomask is used and a metal film is selectively etched, whereby one wiring having a side face, the shape (specifically, an angle with respect to a principal plane of a substrate) of which is different depending on a place, is obtained.

Abstract: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.

Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

Abstract: Methods of densifying a porous ultra-low-k (ULK) dielectric material by using gas-cluster ion-beam processing are disclosed. Methods for gas-cluster ion-beam etching, densification, pore sealing and ashing are described that allow simultaneous removal of material and densification of the ULK interfaces. A novel ULK dual damascene structure is disclosed with densified interfaces and no hard-masks.