Abstract: A method of manufacturing a structure includes a first step of forming, on a monocrystal silicon substrate having a (100) surface as a principal surface, a basic etching mask corresponding to a target shape and having at least a first structure with a projecting corner and a second structure adjoining the first structure with an opening intervening therebetween, and a correction etching mask extending from the projecting corner of an etching mask of the first structure and connected to an etching mask of the second structure, and a second step of performing anisotropic etching of the monocrystal silicon substrate having the basic etching mask and the correction etching mask to form the target shape.

Abstract: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.

Abstract: Provided are a photoresist coating apparatus and a method of coating photoresist using the same. The apparatus includes a photoresist supply line through which photoresist is supplied. A fluid control valve is connected to the photoresist supply line to control the flow of the photoresist. A nozzle assembly is connected to the photoresist supply line at a rear end of the fluid control valve. The nozzle assembly includes a nozzle located above the center of a semiconductor wafer loaded in a photoresist coating unit to spray the photoresist. A camera is located outside the photoresist coating unit to monitor the shape or spraying amount of the nozzle located at the tip of the nozzle assembly. A controller converts data monitored by the camera into an electric signal and processes the electric signal.

Abstract: A method for fabricating a semiconductor device and an equipment for fabricating the semiconductor device are described. According to the method and the equipment, a semiconductor substrate is irradiated with a particle beam through an opening formed in a thin film portion of a stencil mask having the thin film portion and a supporting portion supporting the thin film portion. The method and the equipment are controlled so that the supporting portion of the stencil mask can be irradiated with the fringe of the particle beam. As a result, the method and the equipment provide suppressing deterioration such as deformation or breakage of the stencil mask.

Abstract: In order to produce doping regions (DG) in a substrate (S) having different dopings with the aid of a single mask (DM) different mask regions are provided which have elongated mask openings (MO) having different orientations relative to the spatial direction of an oblique implantation. The substrate is rotated between the first and second oblique implantations, wherein during the first oblique implantation maximum and minimum shadings in the different mask regions are opposite one another and the conditions are precisely reversed during the second oblique implantation after the rotation of the substrate.

Abstract: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.

Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.

Abstract: A method for fabricating a semiconductor device includes forming an amorphous carbon layer over a substrate, forming a hard mask pattern over the amorphous carbon layer, and etching the amorphous carbon layer with an etching gas including sulfur (S) using the hard mask pattern as an etch barrier. Deformation of the amorphous carbon patterns is prevented by hardening the sidewalls of the amorphous carbon layer exposed during etching of the amorphous carbon layer. Therefore, when the etch target layer is etched with the amorphous carbon patterns having a vertical shape, pattern uniformity of the etch target pattern can be improved.

Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Abstract: There is provided a photo mask for forming a specific pattern and a specific pattern formed using the photo mask. Unlike in a related method of forming a specific pattern using a photo mask including cell lines and pad lines, the photo mask is manufactured with cell lines and pad lines, the pad lines each including at least one space line. The photoresist layer is exposed and developed using the photomask to form the photoresist pattern. The etched layer is etched in accordance with the photoresist pattern to form the specific pattern. Therefore, it is possible to improve the pattern uniformity of the semiconductor device and thus to improve yield.

Abstract: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to the interface surface. A metal film is then bonded to the adhesive, thereby easily adapting the interface surface for bonding to the liquid metal.

Abstract: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.

Abstract: Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas. A first portion of the silicon oxide film is deposited using the high-density plasma at a deposition rate between 900 and 6000 ?/min and with a deposition/sputter ratio greater than 30. The deposition/sputter ratio is defined as a ratio of a net deposition rate and a blanket sputtering rate to the blanket sputtering rate. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched. A second portion of the silicon oxide film is deposited over the etched portion of the silicon oxide film.

Abstract: One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Abstract: A method is provided for fabricating current-carrying formation on substrates. The method includes providing a substrate including a layer of a voltage switchable dielectric material, forming a mask over the layer of the voltage switchable dielectric material, and forming an electrically conductive layer. The mask includes gaps and the electrically conductive layer is formed in the gaps. The voltage switchable dielectric material has a characteristic voltage and the electrically conductive layer is formed by applying a voltage in excess of the characteristic voltage to the substrate and depositing the electrically conductive material through an electrochemical process such as electroplating.

Abstract: A method of fabricating a grayscale reticule includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticule; and using the reticule to pattern a microlens array.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based on measured results.

Abstract: A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern which forms a channel of the thin film transistor and overlaps along the data line; a passivation film covering the data line and the thin film transistor; and a pixel electrode on the gate insulating film in a pixel hole of the pixel area that penetrates the passivation film and connected to the thin film transistor, the pixel electrode on an inclined side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film and having a thickness that decreases as it goes up the side surface of the passivation film.

Abstract: A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers.

Abstract: A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment, the opening in the hard mask layer is formed at the minimum limits allowable by optical lithography. A conformal spacer layer is formed over the hard mask layer and on the sidewalls of the hard mask, then spacer etched to form first and second cross-sectional spacers along the first and second sidewalls in the patterned hard mask layer. The hard mask and spacers are preferably formed from amorphous carbon. The layer to be etched is etched using the hard mask layer and the spacers as a pattern, then the hard mask layer and spacers are removed.

Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.

Abstract: A semiconductor device comprises a semiconductor substrate including a scribe lane, and a metal layer disposed over the semiconductor substrate. The metal layer is formed over the overlay vernier by a sputtering method. The overlay vernier comprises a bar type mother vernier formed in the scribe lane. The overlay vernier has a sloped profile.

Abstract: A method of manufacturing an array substrate of a transflective liquid crystal display is provided. Utilizing backward exposure and half-tone photo-mask to reduce the number of photo-masks used in the manufacturing process, only three to four photo-masks are used to manufacture a transflective liquid crystal display.

Abstract: When annealing of a semiconductor film is conducted using a plurality of lasers, each of the distances between laser irradiation regions is different. When a lithography step is conducted in accordance with a marker which is formed over a substrate in advance after the step, light-exposure is not correctly conducted to a portion crystallized by laser. By using a laser irradiation region obtained on a laser irradiation step as a marker, light-exposure is conducted by making a light-exposure position of a stepper coincide with a large grain size region in the laser irradiation region. A large grain size region and a poorly crystalline region are detected by utilizing a thing that scattering intensity of light is different between the large grain size region and the poorly crystalline region, thereby determining a light-exposure position.

Abstract: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is etched, and then the first metal layer is etched. Thus, an outer connecting pad in the connecting region and a bottom electrode in the capacitor region are formed simultaneously, and a part of the insulating layer on the bottom electrode remains. Thereafter, a dielectric layer is deposited, and then a dual damascene copper process is performed to form an inductance structure and a top electrode of a capacitor in the dielectric layer simultaneously. Next, a passive layer is deposited and an etching process is thereafter performed to expose the outer connecting pad.

Abstract: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch. First and second overcoats are formed over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively. The first and second overcoats define a space therebetween and are configured to expose an underlying layer. A filling layer is formed to fill the space defined between the first and second overcoats. The first and second overcoats are removed to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch.

Abstract: According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps each associated with a particular one of a plurality of circuit features. Each map maps an illumination field comprising a plurality of point sources and indicates, in terms of a process metric and for each point source, a level of feature quality that will result from using the each point source to image the each circuit feature. The method also includes identifying, based on the maps, a group of one or more of the point sources that, if used to image the circuit features onto a target surface, will result in an overall feature quality level equal to or greater than a predetermined quality threshold.

Abstract: A method for forming a PECVD deposited ashable hardmask (AHM) with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks having the property of high selectivity of the hard mask film to the underlying layers for successful integration of the film, and are suitable for use with 193 nm generation and below lithography schemes wherein high selectivity of the hard mask to the underlying layers is required. The low temperature, low H films are produced by use of a pulsed film hydrocarbon precursor plasma treatment that reduces the amount of hydrogen incorporated in the film and therefore drives down the etch rate of the hard mask thus increasing the selectivity. The lower temperature process also allows reduction of the overall thermal budget for a wafer.

Abstract: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

Abstract: A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area of the photomask. Also, a method for forming test structures is disclosed in which the photomask is exposed to transfer the test pattern to a semiconductor substrate. The process step that is associated with the test pattern is then performed, forming a test structure on the semiconductor substrate. By utilizing blading areas of photomasks and including test patterns for different process steps on the same photomask, more test structures can be obtained, without the need to generate additional photomasks for testing purposes.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: The invention comprises a method of fabricating a three-axis accelerometer. A first wafer having a first and a second major surface provided with etching at least two cavities in the first major surface of the first wafer and patterning metal onto the first major surface of the first wafer to form electrical connections for a third accelerometer. A second wafer, etching a portion of a first major surface of the second wafer and bonding the first major surface of the first wafer to the first major surface of the second wafer. The etching and bonding of the surfaces deposit and pattern metallizating, and deposit and pattern a masking layer on the second major surface of the second wafer, defining the shape of a first, a second and the third accelerometer. The first and second accelerometers are formed over the cavities etched in the first major surface of the first wafer.

Abstract: An object of the invention is to provide a resist composition which is possible to form a film by using a drawing means and which functions as a protective film used at the time of etching, adding impurities, or the like. In addition, an object is also to provide a manufacturing step of a semiconductor device in which a substance with high safety and that is easily treated can be used as a peeling solution, and which pays attention to an environment. A resist composition of the invention contains water-soluble homopolymer, water, or a solvent that has compatibility with water and can dissolve the water-soluble homopolymer. In addition, a method for manufacturing the semiconductor device of the invention has a step of removing the protective film formed by discharging the resist composition of the invention by using a drawing means with water after using it.

Abstract: A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure heat-treatment, and a complicated structure can be formed using the photoresist.

Abstract: A method of forming a polycrystalline silicon layer includes: disposing a mask over the amorphous silicon layer, the mask having a plurality of transmissive regions, the plurality of transmissive regions being disposed in a stairstep arrangement spaced apart from each other in a first direction and a second direction substantially perpendicular from the first direction, each transmissive region having a central portion and first and second side portions that are adjacent to opposite ends of the central portion along the first direction, and wherein each of the portions has a length along the first direction and a width along the second direction, and wherein the width of first and second portions decreases away from the central portion along the first direction; irradiating a laser beam onto the amorphous silicon layer a first time through the mask to form a plurality of first irradiated regions corresponding to the plurality of transmissive regions, each first irradiated region having a central portion, and

Abstract: A drive unit is described for switching circuit breakers on and off, in particular disconnecting switches and/or grounding switches of medium-voltage switchgear. The drive unit includes a reversible d.c. motor and a switching device containing two separately drivable and interlocked reversing switches, one assigned to each direction of rotation of the d.c. motor, their contacts performing the current reversal on the windings of the d.c. motor as required to reverse the direction of rotation. The drive unit further includes power contactors whose contacts have the required switching capacity for load switching. The all-or-nothing relays and safety switches are implemented by uniform low-power relays representing the direction of rotation, each having at least two electrically isolated relay contacts connected in parallel and also having an equalizing capacitor connected in parallel to each. Such drive units are used in connection with switchgear for power transmission and distribution.

Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

Abstract: A method which lower the series resistance of photosensitive devices includes providing a transparent film of a first electrically conductive material arranged on a transparent substrate; depositing and patterning a mask over the first electrically conductive material, such that openings in the mask have sloping sides which narrow approaching the substrate; depositing a second electrically conductive material directly onto the first electrically conductive material exposed in the openings of the mask, at least partially filling the openings; stripping the mask, leaving behind reentrant structures of the second electrically conductive material which were formed by the deposits in the openings of the mask; after stripping the mask, depositing a first organic material onto the first electrically conductive material in between the reentrant structures; and directionally depositing a third electrically conductive material over the first organic material deposited in between the reentrant structures, edges of the r

Abstract: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or a softening point of the resist pattern; and a third step of transferring the resist pattern after the plasma processing to the etched layer by etching, and forming the pattern of the etched layer.

Abstract: An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

Abstract: The invention relates to a method for applying rewiring to a panel. For this purpose, a panel is provided which has a coplanar overall upper side of an upper side of a plastic compound and the upper sides of semiconductor chips. The method provides a rewiring layer with implementation of external contacts and rewiring lines which, by means of a two-stage exposure step, compensates for position errors of the semiconductor chips in the component positions of the panel.

Abstract: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features using an off-axis lithography method. A portion of the pattern for the array of features is transferred to the first hard mask. The first hard mask is then used as a mask to pattern the material layer.

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while baring the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.