Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.

Abstract: Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.

Abstract: In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.

Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.

Abstract: A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.

Abstract: A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.

Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.

Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.

Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.

Abstract: A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.

Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.

Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.

Abstract: A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.

Abstract: In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A method for forming a thin film photovoltaic device having patterned electrode films includes providing a soda lime glass substrate with an overlying lower electrode layer comprising a molybdenum material. The method further includes subjecting the lower electrode layer with one or more pulses of electromagnetic radiation from a laser source to ablate one or more patterns associated with one or more berm structures from the lower electrode layer. Furthermore, the method includes processing the lower electrode layer comprising the one or more patterns using a mechanical brush device to remove the one or more berm structures followed by treating the lower electrode layer comprising the one or more patterns free from the one or more berm structures. The method further includes forming a layer of photovoltaic material overlying the lower electrode layer and forming a first zinc oxide layer overlying the layer of photovoltaic material.

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.

Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and secon

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.

Abstract: A method for manufacturing a solid-state imaging device, in which a photoelectric conversion portion to receive light with a light-receiving surface and generate a signal charge is disposed in a substrate, includes the steps of forming a metal light-shield layer above the substrate and in a region other than a region corresponding to the light-receiving surface, forming a light-reflection layer above the metal light-shield layer, and forming a photoresist pattern layer from a negative type photoresist film formed above the light-reflection layer, by conducting an exposing treatment and a developing treatment, wherein in the forming of the light-reflection layer, the light-reflection layer includes a shape corresponding to a pattern shape of the photoresist pattern layer, and the light-reflection layer is formed in such a way as to reflect exposure light to the photoresist film in conduction of the exposing treatment in the forming of the photoresist pattern layer.

Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Abstract: Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract: A photoelectric conversion element includes a first electrode, a second electrode, and a photoelectric conversion element provided between the first electrode and the second electrode. The photoelectric conversion element includes a polymer. The polymer includes at least one light absorber which absorbs light and generates at least one kind of carrier. An end part of the polymer combines with a surface, which faces the second electrode, of the first electrode.