Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Abstract: The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a photocatalyst-containing property variable layer which is formed on the base material, comprises at least a photocatalyst and a binder, and has a property variable by action of the photocatalyst based on irradiation with energy; and an energy radiating process of radiating energy onto the patterning substrate at an intensity of 0.1 to 10 mW/cm2, thereby forming a property variable pattern in which the property of the photocatalyst-containing property variable layer is varied.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided over the second layer to define an X or Y dimension of the contact/via hole. A second photoresist pattern is provided over the second layer to define an opposite dimension of the contact/via hole. First and second pattern dimensions are measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed to form the contact/via hole. If the photoresist pattern is not within a desired tolerance, the etching process may be adjusted to ensure the cavity will have the desired dimensions.

Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.

Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: A circuitry sheet (322) comprising an electronic device layer stack (304) containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method (200) that includes the steps of forming the device layer stack on a temporary substrate (300), removing material from both sides of the device layer stack, and then attaching a permanent substrate (348) to the device layer stack. The method uses one or more resist layers (600) that may be activated simultaneously and independently to impart distinct circuit pattern images (603, 608, 612) into each of a plurality of image levels (612, 616, 620) within each resist layer, thereby obviating repetitive sequential exposure, registration and alignment steps.

Abstract: A photosensitive resist (100) for coating on a semiconductor substrate or a mask comprises a photo acid generator (D), a solvent (E) and at least two different base polymers, of which a first base polymer comprises cycloaliphatic parent structures (A) which substantially absorb incident light at 248 nm and are substantially transparent to incident light at 193 nm, and a second base polymer comprises aromatic parent structures (B) which substantially absorb incident light at 193 nm and are substantially transparent to incident light at 248 nm. If such a resist (100) is applied in a coat thickness of from 50 to 400 nm to a substrate and the proportion of the second base polymer having the aromatic parent structure is between 1 and 25 mol %, a relatively high structure contrast, better stability to etching and a reduction of defects are advantageously achieved in an exposure at a wavelength of 193 nm. Exposure over the entire depth range of the resist (100) is ensured thereby.

Abstract: The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.