Epitaxial Deposition Of Group Iii-v Compound (epo) Patents (Class 257/E21.097)
E Subclasses
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Publication number: 20100240198Abstract: A method for fabricating a semiconductor device includes growing an AlN layer by MOVPE in which a nitrogen-source flow ratio at a far side from a substrate is set lower than that at a near side, the nitrogen-source flow ratio being a ratio of a flow rate of a nitrogen source to a total flow rate of growth gas; and growing a GaN-based semiconductor layer on the AlN layer by MOVPE.Type: ApplicationFiled: March 19, 2010Publication date: September 23, 2010Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Mitsunori Yokoyama
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Patent number: 7799592Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.Type: GrantFiled: September 26, 2007Date of Patent: September 21, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 7790584Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.Type: GrantFiled: October 7, 2008Date of Patent: September 7, 2010Assignee: Samsung Led Co., Ltd.Inventors: Ho Sun Paek, Jeong Wook Lee, Youn Joon Sung
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Patent number: 7776634Abstract: A semiconductor laser with a semiconductor substrate, a laser layer arranged on the semiconductor substrate, a waveguide arranged parallel to the laser layer and a strip shaped grating structure is disclosed. The laser layer, the waveguide and the grating are arranged in a configuration which results in weak coupling between the laser light and the grating structure, so that the laser light interacts with an increased number of grating elements. A process for the production of such a semiconductor laser is also disclosed.Type: GrantFiled: November 5, 2008Date of Patent: August 17, 2010Assignee: Nanoplus GmbHInventors: Johann Peter Reithmaier, Lars Bach
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Patent number: 7759219Abstract: A method of manufacturing a nitride semiconductor device includes the steps of; forming a stripping layer including In on a substrate; forming a nitride semiconductor layer on the stripping layer; causing a decomposition of the stripping layer by increasing a temperature of the stripping layer; irradiating the stripping layer with laser light; and separating the nitride semiconductor layer from the substrate.Type: GrantFiled: September 21, 2006Date of Patent: July 20, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Yasumitsu Kunoh, Kunio Takeuchi
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Patent number: 7749828Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: GrantFiled: March 3, 2006Date of Patent: July 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
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Patent number: 7732301Abstract: A method of making a bonded intermediate substrate includes forming a weak interface in a GaN source substrate by implanting ions into an N-terminated surface of the GaN source substrate, bonding the N-terminated surface of the GaN source substrate to a handle substrate, and exfoliating a thin GaN single crystal layer from the source substrate such that the thin GaN exfoliated single crystal layer remains bonded to the handle substrate and a Ga-terminated surface of the thin GaN single crystal layer is exposed. The method further includes depositing a capping layer directly onto the exposed surface of the thin GaN single crystal layer, and annealing the thin GaN single crystal layer in a nitrogen containing atmosphere after depositing the capping layer. The in-plane strain present in the thin GaN single crystal layer after the annealing is reduced relative to an in-plane strain present in said layer prior to the annealing.Type: GrantFiled: April 18, 2008Date of Patent: June 8, 2010Inventors: Thomas Henry Pinnington, James M. Zahler, Young-Bae Park, Corinne Ladous, Sean Olson
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Patent number: 7732306Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.Type: GrantFiled: July 25, 2008Date of Patent: June 8, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Chantal Arena, Subhash Mahajan, Ranjan Datta
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Patent number: 7723217Abstract: The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex upwards the base substrate and the gallium nitride film and create cracks in the gallium nitride film; (b) growing a gallium nitride single crystalline layer on the crack-created gallium nitride film located on the convex upward base substrate; and (c) cooling a resultant product having the grown gallium nitride single crystalline layer to make the convex upward resultant product flat or bend convex downwards the convex upward resultant product and at the same time to self-split the base substrate and the gallium nitride single crystalline layer from each other at the crack-created gallium nitride film interposed therebetween.Type: GrantFiled: December 10, 2008Date of Patent: May 25, 2010Assignee: Siltron Inc.Inventors: Ho-Jun Lee, Doo-Soo Kim, Dong-Kun Lee, Yong-Jin Kim
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Patent number: 7696019Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.Type: GrantFiled: March 9, 2006Date of Patent: April 13, 2010Assignee: Infineon Technologies AGInventor: Jin-Ping Han
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Patent number: 7682944Abstract: A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out lateral epitaxial overgrowth to form a bridged lateral overgrowth formation overlying the trench cavity. The bridged lateral overgrowth formation provides a substrate surface on which epitaxial layers can be grown in the fabrication of microelectronic devices such as laser diodes, high electron mobility transistors, ultraviolet light emitting diodes, and other devices in which low dislocation density is critical. The epitaxial substrate structures of the invention can be formed without the necessity for deep trenches, such as are required in conventional Pendeo epitaxial overgrowth structures.Type: GrantFiled: December 14, 2007Date of Patent: March 23, 2010Assignee: Cree, Inc.Inventors: George R. Brandes, Arpan Chakraborty, Shuji Nakamura, Monica Hansen, Steven Denbaars
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Publication number: 20100032718Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.Type: ApplicationFiled: August 11, 2008Publication date: February 11, 2010Inventors: Chia-Lin Yu, Ding-Yuan Chen, Chen-Hua Yu, Wen-Chih Chiou
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Patent number: 7659137Abstract: A fabrication method of fabricating a structure capable of being used for generation or detection of electromagnetic radiation includes a forming step of forming a layer containing a compound semiconductor on a substrate at a substrate temperature below about 300° C., a first heating step of heating the substrate with the layer in an ambience containing arsenic, and a second heating step of heating the substrate with the layer at the substrate temperature above about 600° C. in a gas ambience incapable of chemically reacting on the compound semiconductor. Structures of the present invention capable of being used for generation or detection of electromagnetic radiation can be fabricated using the fabrication method by appropriately regulating the substrate temperature, the heating time, the gas ambience and the like in the second heating step.Type: GrantFiled: March 25, 2005Date of Patent: February 9, 2010Assignee: Canon Kabushiki KaishaInventors: Shintaro Kasai, Toshihiko Ouchi, Masatoshi Watanabe, Mitsuru Ohtsuka, Taihei Mukaide
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Patent number: 7632742Abstract: A Pendeo-epitaxy growth substrate and a method of manufacturing the same are provided. The Pendeo-epitaxy growth substrate includes a substrate, a plurality of pattern areas formed on the substrate in a first direction for Pendeo-epitaxy growth, and at least one solution blocking layer contacting the plurality of pattern areas and formed on the substrate in a second direction, thereby preventing contamination of a semiconductor device due to air gaps and reducing the percentage defects of the semiconductor device during a Pendeo-epitaxy growth process.Type: GrantFiled: January 9, 2007Date of Patent: December 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-sun Paek, Tae-hoon Jang, Youn-joon Sung, Tan Sakong, Min-ho Yang
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Patent number: 7629237Abstract: A method of MBE growth of a semiconductor layer structure comprises growing a first (Al,Ga)N layer (step 13) over a substrate at the first substrate temperature (T1) using ammonia as the nitrogen precursor. The substrate is then cooled (step 14) to a second-substrate temperature (T2) which is lower than the first substrate temperature. An (In,Ga)N quantum well structure is then grown (step 15) over the first (Al,Ga)N layer by MBE using ammonia as the nitrogen precursor. The supply of ammonia to the substrate is maintained continuously during the first growth step, the cooling step, and the second growth step. After completion of the growth of the (In,Ga)N quantum well structure, the substrate may be heated to a third temperature (T3) which is greater than the second substrate temperature (T2). A second (Al,Ga)N layer is then grown over the (In,Ga)N quantum well structure (step 17).Type: GrantFiled: August 18, 2003Date of Patent: December 8, 2009Assignee: Sharp Kabushiki KaishaInventors: Valerie Bousquet, Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan
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Publication number: 20090239356Abstract: A device manufacturing method includes a buffer layer forming step of forming a buffer layer on an underlying substrate, a mask pattern forming step of forming, on the buffer layer, a mask pattern which partially covers the buffer layer, a growth step of growing a group III nitride crystal from regions exposed by the mask pattern on the surface of the buffer layer, thereby forming a structure in which a plurality of crystal members are arranged with gaps therebetween so as to partially cover the buffer layer and the mask pattern, a channel forming step of forming a channel, to supply a second etchant for the buffer layer to the buffer layer, by selectively etching the mask pattern using a first etchant for the mask pattern, and a separation step of separating the plurality of crystal members from the underlying substrate and separating the plurality of crystal members from each other by supplying the second etchant to the buffer layer through the gaps and the channel and selectively etching the buffer layer.Type: ApplicationFiled: March 17, 2009Publication date: September 24, 2009Inventors: Takafumi Yao, Meoung-Whan Cho
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Patent number: 7585752Abstract: Chemical vapor deposition processes utilize chemical precursors that allow for the deposition of thin films to be conducted at or near the mass transport limited regime. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, a higher order silane is employed to deposit thin films containing silicon that are useful in the semiconductor industry in various applications such as transistor gate electrodes.Type: GrantFiled: October 12, 2004Date of Patent: September 8, 2009Assignee: ASM America, Inc.Inventors: Michael A. Todd, Mark Hawkins
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Publication number: 20090209091Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.Type: ApplicationFiled: February 13, 2009Publication date: August 20, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Fumitaka Sato, Seiji Nakahata
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Patent number: 7576351Abstract: A nitride semiconductor light generating device comprises an n-type gallium nitride based semiconductor layer, a quantum well active layer including an InX1AlY1Ga1-X1-Y1N (1>X1>0, 1>Y1>0) well layer and an InX2AlY2Ga1-X2-Y2N (1>X2>0, 1>Y2>0) barrier layer, an InX3AlY3Ga1-X3-Y3N (1>X3>0, 1>Y3>0) layer provided between the quantum well active layer and the n-type gallium nitride based semiconductor layer, and a p-type AlGaN layer having a bandgap energy greater than that of the InX2AlY2Ga1-X2-Y2N barrier layer. The indium composition X3 is greater than an indium composition X1. The indium composition X3 is greater than an indium composition X2. The aluminum composition Y2 is smaller than an aluminum composition Y3. The aluminum composition Y1 is smaller than an aluminum composition Y3. The oxygen concentration of the quantum well active layer is lower than that of the InX3AlY3Ga1-X3-Y3N layer.Type: GrantFiled: January 26, 2007Date of Patent: August 18, 2009Assignees: Sumitomo Electric Industries, Ltd., RikenInventors: Takashi Kyono, Hideki Hirayama
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Patent number: 7560296Abstract: A method of manufacturing a low defect density GaN material comprising at least two step of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially compentent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence.Type: GrantFiled: September 11, 2006Date of Patent: July 14, 2009Assignee: LumilogInventors: Eric Frayssinet, Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart
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Patent number: 7550368Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.Type: GrantFiled: May 24, 2006Date of Patent: June 23, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Sugawara, Tsunenori Hiratsuka
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Publication number: 20090155986Abstract: The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex upwards the base substrate and the gallium nitride film and create cracks in the gallium nitride film; (b) growing a gallium nitride single crystalline layer on the crack-created gallium nitride film located on the convex upward base substrate; and (c) cooling a resultant product having the grown gallium nitride single crystalline layer to make the convex upward resultant product flat or bend convex downwards the convex upward resultant product and at the same time to self-split the base substrate and the gallium nitride single crystalline layer from each other at the crack-created gallium nitride film interposed therebetween.Type: ApplicationFiled: December 10, 2008Publication date: June 18, 2009Applicant: SILTRON INC.Inventors: Ho-Jun Lee, Doo-Soo Kim, Dong-Kun Lee, Yong-Jin Kim
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Patent number: 7537944Abstract: An object of the present invention is to provide an efficient method for manufacturing a p-type group III nitride semiconductor that has adequate carrier concentration and a surface with a low occurrence of crystal damage. The inventive method for manufacturing a p-type group III nitride semiconductor comprises: (a) growing a group III nitride semiconductor containing a p-type dopant at 1000° C. or higher in an atmosphere containing H2 gas and/or NH3 gas; and (b) after the growth of the group III nitride semiconductor, substituting the H2 gas and NH3 gas with an inert gas at a temperature higher than 800° C. while reducing the temperature.Type: GrantFiled: November 4, 2004Date of Patent: May 26, 2009Assignee: Showa Denko K.K.Inventor: Masato Kobayakawa
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Patent number: 7531397Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.Type: GrantFiled: January 3, 2008Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
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Patent number: 7510957Abstract: A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device.Type: GrantFiled: December 4, 2006Date of Patent: March 31, 2009Assignee: International Rectifier CorporationInventors: Robert Beach, Paul Bridger
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Patent number: 7498244Abstract: The present invention relates to a method for fabricating a gallium nitride(GaN) based nitride layer including a step of forming a silicon carbide buffer layer on a substrate, a step of forming a wetting layer having a composition of In(x1)Ga(y1)N (0<x1?1, 0?y1<1, x1+y1=1) on the silicon carbide buffer layer, and a step of forming a nitride layer containing gallium and nitrogen on the wetting layer, thereby can implement an opto-electronic device of high efficiency and high reliability.Type: GrantFiled: August 21, 2004Date of Patent: March 3, 2009Assignees: Epivalley Co., Ltd., Samsung Electro-Mechanics Co., Ltd.Inventors: Soo Kun Jeon, Moon Sik Jang
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Patent number: 7491627Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.Type: GrantFiled: August 22, 2007Date of Patent: February 17, 2009Assignee: International Rectifier CorporationInventors: Robert Beach, Paul Bridger
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Publication number: 20090001519Abstract: Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.Type: ApplicationFiled: September 9, 2008Publication date: January 1, 2009Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE JAPAN SCIENCE AND TECHNOLOGY CENTERInventors: Benjamin A. Haskell, Paul T. Fini, Shigemasa Matsuda, Michael D. Craven, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Publication number: 20090001422Abstract: There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C.Type: ApplicationFiled: October 19, 2007Publication date: January 1, 2009Applicant: ADVANTEST CORPORATIONInventors: Junichi OKAYASU, Takuya OIZUMI
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Patent number: 7462893Abstract: A method of fabricating a thick gallium nitride (GaN) layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCI and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of forming the porous GaN layer and the thick GaN layer in-situ proceeds in a single chamber. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN etching and growth are performed using an HVPE process gas such that costs are greatly reduced.Type: GrantFiled: October 11, 2006Date of Patent: December 9, 2008Assignee: Samsung Corning Co., Ltd.Inventors: Jai-yong Han, Jun-sung Choi, In-jae Song
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Patent number: 7439165Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.Type: GrantFiled: April 6, 2005Date of Patent: October 21, 2008Assignee: Agency for Sceince, Technology and ReasearchInventors: Patrick Guo Oiang Lo, Lakshmi Kanta Bera, Wei Yip Loh, Balakumar Subramanian, Narayanan Balasubramanian
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Publication number: 20080188065Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: August 7, 2008Applicant: Centre National De La Recherche Scientifique (CNRS)Inventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Patent number: 7407865Abstract: An epitaxial growth method for forming a high-quality epitaxial growth semiconductor wafer is provided. The method includes forming a single crystalline layer on a single crystalline wafer; forming a mask layer having nano-sized dots on the single crystalline layer; forming a porous buffer layer having nano-sized pores by etching the mask layer and the surface of the single crystalline layer; annealing the porous buffer layer; and forming an epitaxial material layer on the porous buffer layer using an epitaxial growth process.Type: GrantFiled: January 5, 2006Date of Patent: August 5, 2008Assignee: Samsung Corning Co., Ltd.Inventor: Sung-soo Park
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Patent number: 7399692Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.Type: GrantFiled: September 29, 2006Date of Patent: July 15, 2008Assignee: International Rectifier CorporationInventors: Zhi He, Robert Beach
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Patent number: 7361576Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.Type: GrantFiled: May 31, 2006Date of Patent: April 22, 2008Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Bilge M. Imer, James S. Speck, Steven P. DenBaars
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Publication number: 20080050894Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: February 28, 2008Applicant: PICOGIGA INTERNATIONAL SASInventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Patent number: 7332417Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.Type: GrantFiled: January 27, 2004Date of Patent: February 19, 2008Assignee: AmberWave Systems CorporationInventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky T. Yang, Christopher W. Leitz
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Patent number: 7288430Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.Type: GrantFiled: June 24, 2005Date of Patent: October 30, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnolgoiesInventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
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Patent number: 7253499Abstract: A III-V group nitride system semiconductor self-standing substrate has III-V group nitride system semiconductor single crystal with a hexagonal crystal system crystalline structure. The substrate is provided with a polished surface at every position of which crystal orientation perpendicular to the substrate surface is inclined 0.09 degrees or more from the C-axis direction of the substrate.Type: GrantFiled: September 30, 2004Date of Patent: August 7, 2007Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
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Patent number: 7250360Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.Type: GrantFiled: March 2, 2005Date of Patent: July 31, 2007Assignee: Cornell Research Foundation, Inc.Inventors: James R. Shealy, Joseph A. Smart
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Patent number: 7245017Abstract: The liquid discharge head has a three-dimensional structure which defines a space including a pressure chamber filled with liquid and a flow channel for supplying the liquid to the pressure chamber, the three-dimensional structure being formed by depositing a composition material on a substrate according to a deposition method, and a drive element which causes discharge of the liquid from the pressure chamber through a nozzle.Type: GrantFiled: March 3, 2005Date of Patent: July 17, 2007Assignee: Fujifilm CorporationInventors: Yasukazu Nihei, Tsuyoshi Mita
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Patent number: 7220658Abstract: Lateral epitaxial overgrowth (LEO) of non-polar a-plane gallium nitride (GaN) films by hydride vapor phase epitaxy (HVPE) results in significantly reduced defect density.Type: GrantFiled: July 15, 2003Date of Patent: May 22, 2007Assignee: The Regents of the University of CaliforniaInventors: Benjamin A Haskell, Michael D. Craven, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 7208393Abstract: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.Type: GrantFiled: May 31, 2005Date of Patent: April 24, 2007Assignee: The Regents of the University of CaliforniaInventors: Benjamin A. Haskell, Melvin B. McLaurin, Steven P. DenBaars, James Stephen Speck, Shuji Nakamura
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Patent number: 7125735Abstract: A method of fabricating a semiconductor device includes the steps of forming a step region having a mesa shape in a direction of <011> or <0-11> on a (100) plane of an InP-based compound semiconductor crystal, and burying the step region with InP-based buried layers grown by vapor-phase growth by supplying a base gas to which a chlorinated organic compound is added, the organic chlorine compound including at least two carbon atoms, and each of the carbon atoms is bonded to one chlorine (Cl) atom in one molecule. The chlorinated organic compound is any one of 1,2-dichloroethane, 1,2-dichloropropane, and 1,2-dichloroethylene.Type: GrantFiled: February 8, 2005Date of Patent: October 24, 2006Assignee: Eudyna Devices, Inc.Inventor: Tatsuya Takeuchi