Comprising Layer Having Ferroelectric Properties (epo) Patents (Class 257/E21.208)
  • Patent number: 7229914
    Abstract: Wiring layers through that come into direct contact with an electrode of a ferroelectric capacitor provide a wiring layer structure configured so that the characteristic of the ferroelectric substance is not degraded by production of a reducing agent. One of coating layers through is provided on the periphery of the Al main wiring layer. A single Ti film or TiN film or a combination of both is used as the coating film. The TiN film suppresses reaction between water and aluminum. The Ti film occludes hydrogen. Therefore, the coating layer provided on the periphery of the Al wiring layer inhibits water or molecular hydrogen from entering the Al wiring layer from the outside and therefore there is no degradation of the characteristics of the ferroelectric capacitor.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 12, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tomomi Yamanobe
  • Publication number: 20070128736
    Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
    Type: Application
    Filed: January 10, 2006
    Publication date: June 7, 2007
    Inventors: Vincent Chang, Fong-Yu Yen, Peng-Soon Lim, Jin Ying, Hun-Jan Tao
  • Patent number: 7224040
    Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: May 29, 2007
    Assignee: Gennum Corporation
    Inventors: Ivoyl P. Koutsaroff, Mark Vandermeulen, Andrew Cervin-Lawry, Atin J. Patel
  • Patent number: 7208786
    Abstract: A memory device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. The method of data storage and retrieval comprising the steps of: providing a layer of ferroelectric material, providing a layer of piezoelectric material, clamping the two layers together, storing data by internally polarising the ferroelectric material in one of two stable directions in accordance with the data to be stored, and retrieving stored data by applying a non-polarising voltage to one layer and detecting a resultant voltage from the other layer. Preferably, the piezoelectric material is implemented as a ferroelectric material.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: April 24, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Daping Chu
  • Patent number: 7205595
    Abstract: An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: Mukul P. Renavikar, Gudbjorg H. Oskarsdottir
  • Patent number: 7183120
    Abstract: A method for fabricating a magnetoresistive device having at least one active region, which may be formed into a magnetic memory bit, sensor element and/or other device, is provided. In forming the magnetoresistive device, a magnetoresistive stack, such as a giant magnetoresistive stack, is formed over a substrate. In addition, a substantially antireflective cap layer formed from titanium nitride, aluminum nitride, and/or other substantially antireflective material, as opposed to the materials commonly used to form a cap layer, is formed over the magnetoresistive stack. The substantially antireflective cap layer is usable as an etch stop for later processing in forming the magnetic memory bit, sensor element and/or other device.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: February 27, 2007
    Assignee: Honeywell International Inc.
    Inventors: Lonny Berg, Daniel Baseman, Wei (David) DZ Zou
  • Patent number: 7157288
    Abstract: A method of producing a ferroelectric capacitor includes the steps of: preparing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; laminating sequentially a metal layer, a first conductive layer, a ferroelectric layer, and a second conductive layer on the first insulating layer to form a capacitor forming laminated layer; forming an etching mask forming layer with strontium tantalate or strontium niobate; forming a silicon oxide layer on the etching mask forming layer for covering a ferroelectric capacitor forming area; forming an etching mask through wet etching of the etching mask forming layer with the silicon oxide layer; and forming a lamination formed of a barrier metal, a lower electrode, a ferroelectric layer, and an upper electrode through dry etching of the capacitor forming laminated layer with the etching mask.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: January 2, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Ito
  • Patent number: 7148531
    Abstract: A ferromagnetic thin-film based digital memory having a substrate formed of a base supporting an electrically insulating material primary substrate layer in turn supporting a plurality of current control devices each having an interconnection arrangement with each of said plurality of current control devices being separated from one another by spacer material therebetween and being electrically interconnected with information storage and retrieval circuitry. A plurality of bit structures are each supported on and electrically connected to a said interconnection arrangement of a corresponding one of said plurality of current control devices and have magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained of which two are separated by at least one intermediate layer of a nonmagnetic material having two major surfaces on opposite sides thereof.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: December 12, 2006
    Assignee: NVE Corporation
    Inventors: James M. Daughton, James G. Deak, Arthur V. Pohm
  • Patent number: 7105880
    Abstract: The electronic device includes a substrate, a lower conductive film provided on the substrate, a functional film provided on the lower conductive film, and a crystallinity barrier film provided between the lower conductive film and the functional film. The present invention prevents the crystallinity of the functional film being affected by the crystallinity or the material selection of the lower conductive film, so it becomes possible to use a low-cost metal such as aluminum (Al) for the lower conductive film, and to use a low-cost method for forming the film, thereby making it possible to improve the crystallinity of the functional film without using a costly film-formation method such as epitaxial growth. For the crystallinity barrier film, there can be used a material having an amorphous structure.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: September 12, 2006
    Assignee: TDK Corporation
    Inventors: Takao Noguchi, Kenji Inoue, Hisatoshi Saito
  • Patent number: 7078241
    Abstract: Ferroelectric memory devices can be formed by polishing an insulating layer on a plurality of ferroelectric capacitors with a silica slurry to reduce a height of the insulating layer above a surface of the plurality of ferroelectric capacitors so that the surface remains covered by a portion of the insulating layer. The insulating layer can be further polished with a ceria slurry to further reduce the height of the insulating layer and to expose a polishing stop layer on the surface of the plurality of ferroelectric capacitors. Related devices are also disclosed.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: July 18, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-ho Son, Sang-woo Lee
  • Patent number: 7026677
    Abstract: The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at least a part of a magnetic yoke, as compared with the case of formation by a dry film forming method, sufficient thickness and higher dimensional precision can be obtained. Consequently, a more stabilized return magnetic field can be generated and high reliability can be assured. Neighboring memory cells can be disposed at narrower intervals, so that the invention is suitable for realizing higher integration and higher packing density.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 11, 2006
    Assignee: TDK Corporation
    Inventors: Akifumi Kamijima, Hitoshi Hatate