Wet Cleaning Only (epo) Patents (Class 257/E21.228)
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Patent number: 11946148Abstract: Described herein is an etching solution suitable for the selective removal of TiSiN over hafnium oxide from a microelectronic device, which consists essentially of: water; at least one alkaline ammonium compound selected from the group consisting of ammonium hydroxide, a quaternary ammonium hydroxide, ammonium fluoride, and a quaternary ammonium fluoride; at least one peroxide compound; a water-miscible organic solvent; at least one nitrogen containing compound selected from the group consisting of a C4-12 alkylamine, a polyalkylenimine, and a polyamine; and optionally at least one chelating agent.Type: GrantFiled: January 10, 2020Date of Patent: April 2, 2024Assignee: Versum Materials US, LLCInventors: Wen Dar Liu, Yi-Chia Lee
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Patent number: 11942337Abstract: The apparatus includes a support unit to support the substrate in a treatment space of a process chamber, a first fluid supply unit to supply a supercritical fluid having an organic solvent dissolved in the supercritical fluid, to the treatment space, a second fluid supply unit to supply the supercritical fluid having no organic solvent dissolved in the supercritical fluid, to the treatment space, an exhaust unit to exhaust the treatment space, a controller to control the first fluid supply unit, the second fluid supply unit, and the exhaust unit. The controller controls the first and second fluid supply units such that the supercritical fluid having no organic solvent dissolved in the supercritical fluid is supplied to the treatment space through the second fluid supply unit, after the supercritical fluid mixed with the organic solvent is supplied to the treatment space through the first fluid supply unit.Type: GrantFiled: October 6, 2020Date of Patent: March 26, 2024Assignee: SEMES CO., LTD.Inventors: Eui Sang Lim, Young Hun Lee, Jinwoo Jung, Miso Park, Byongwook Ahn, Yong Hee Lee
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Patent number: 11923210Abstract: In an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber; removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber; determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.Type: GrantFiled: August 21, 2019Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Chun Hsu, Shu-Yen Wang, Chui-Ya Peng
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Patent number: 11881831Abstract: A method of manufacture for an acoustic resonator device. The method includes forming a nucleation layer characterized by nucleation growth parameters overlying a substrate and forming a strained piezoelectric layer overlying the nucleation layer. The strained piezoelectric layer is characterized by a strain condition and piezoelectric layer parameters. The process of forming the strained piezoelectric layer can include an epitaxial growth process configured by nucleation growth parameters and piezoelectric layer parameters to modulate the strain condition in the strained piezoelectric layer. By modulating the strain condition, the piezoelectric properties of the resulting piezoelectric layer can be adjusted and improved for specific applications.Type: GrantFiled: January 29, 2020Date of Patent: January 23, 2024Assignee: Akoustis, Inc.Inventors: Shawn R. Gibb, Alexander Y. Feldman, Mark D. Boomgarden, Michael P. Lewis, Ramakrishna Vetury, Jeffrey B. Shealy
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Patent number: 11854841Abstract: The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ji Chen, Chih-Shen Yang, Cheng-Yi Huang
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Patent number: 11817309Abstract: Provided are: a method of producing heated ozone water, the method capable of producing heated ozone water having an extremely high ozone concentration by suppressing a reduction in the ozone concentration in high-concentration heated ozone water; heated ozone water; and a semiconductor wafer-cleaning liquid using the heated ozone water. A method of producing heated ozone water obtained by dissolving ozone in pure water, the method being characterized by including: adjusting a pH of the pure water to 3 or less by adding acid to the pure water; to obtain an acid water, dissolving an ozone gas in the acid water; and heating the pure water, the acid water or the ozone water, to 60° C. or more.Type: GrantFiled: October 23, 2020Date of Patent: November 14, 2023Assignees: TOHOKU UNIVERSITY, NOMURA MICRO SCIENCE CO., LTD.Inventors: Yasuyuki Shirai, Takeshi Sakai, Takayuki Jizaimaru
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Patent number: 11798802Abstract: Methods for removing an oxide film and for cleaning silicon-on-insulator structures are disclosed. The methods may involve immersing the silicon-on-insulator structure in a stripping bath to strip an oxide film from the surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure is immersed in an ozone bath comprising ozone. The ozone-treated silicon-on-insulator structure may be immersed in an SC-1 bath comprising ammonium hydroxide and hydrogen peroxide to clean the structure.Type: GrantFiled: February 11, 2022Date of Patent: October 24, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Qingmin Liu, Haihe Liang, Junting Yang
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Patent number: 11769661Abstract: A substrate processing method includes a first cleaning process and a second cleaning process. In the first cleaning process, a substrate is cleaned with a first cleaning solution. In the second cleaning process, the substrate is cleaned with a second cleaning solution having a lower cleanliness than the first cleaning solution after the first cleaning process.Type: GrantFiled: May 22, 2020Date of Patent: September 26, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Hirofumi Takeguchi, Kazuyoshi Shinohara, Takahisa Otsuka, Suguen Lee
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Patent number: 11752529Abstract: A method for controlling damages in cleaning a semiconductor wafer comprising features of patterned structures, the method comprising: delivering a cleaning liquid over a surface of a semiconductor wafer during a cleaning process; and imparting sonic energy to the cleaning liquid from a sonic transducer during the cleaning process, wherein power is alternately supplied to the sonic transducer at a first frequency and a first power level for a first predetermined period of time and at a second frequency and a second power level for a second predetermined period of time, the first predetermined period of time and the second predetermined period of time consecutively following one another, wherein at least one of the cleaning parameters is determined such that a percentage of damaged features as a result of the imparting sonic energy is lower than a predetermined threshold.Type: GrantFiled: November 15, 2017Date of Patent: September 12, 2023Assignee: ACM Research (Shanghai) Inc.Inventors: Hui Wang, Fufa Chen, Fuping Chen, Jian Wang, Xi Wang, Xiaoyan Zhang, Yinuo Jin, Zhaowei Jia, Liangzhi Xie, Jun Wang, Xuejun Li
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Patent number: 11740559Abstract: Apparatuses and methods are described for removing edge bead on a wafer associated with a resist coating comprising a metal containing resist compositions. The methods can comprise applying a first bead edge rinse solution along a wafer edge following spin coating of the wafer with the metal based resist composition, wherein the edge bead solution comprises an organic solvent and an additive comprising a carboxylic acid, an inorganic fluorinated acid, a tetraalkylammonium compound, or a mixture thereof. Alternatively or additionally, the methods can comprise applying a protective composition to the wafer prior to performing an edge bead rinse. The protective composition can be a sacrificial material or an anti-adhesion material and can be applied only to the wafer edge or across the entire wafer in the case of the protective composition. Corresponding apparatuses for processing the wafers using these methods are presented.Type: GrantFiled: October 11, 2021Date of Patent: August 29, 2023Assignee: Inpria CorporationInventors: Mollie Waller, Brian J. Cardineau, Kai Jiang, Alan J. Telecky, Stephen T. Meyers, Benjamin L. Clark
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Patent number: 11699601Abstract: A substrate processing device includes a processing tank, a substrate holding unit, a fluid supply unit, and a control unit. The processing tank stores a processing liquid for processing a substrate. The substrate holding unit holds the substrate in the processing liquid in the processing tank. The fluid supply unit supplies a fluid to the processing tank. The control unit controls the fluid supply unit. The control unit controls the fluid supply unit such that the fluid supply unit changes supply of the fluid during a period from a start of supply of the fluid to the processing tank storing the processing liquid in which the substrate is immersed to an end of supply of the fluid to the processing tank storing the processing liquid in which the substrate is immersed.Type: GrantFiled: June 27, 2021Date of Patent: July 11, 2023Assignee: SCREEN Holdings Co., Ltd.Inventors: Tomohiro Takahashi, Kei Takechi, Mitsutoshi Sasaki, Takashi Akiyama
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Patent number: 11676828Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a tank, a heater, a bubble supplier, a sensor and a controller. The tank stores a chemical solution for processing a substrate. The heater heats the chemical solution. The bubble supplier supplies bubbles to the chemical solution in the tank. The sensor detects at least one of a concentration of the chemical solution, a water concentration of the chemical solution, specific gravity of the chemical solution and a vapor concentration of a gas discharged from the tank. The controller controls the supply of bubbles by the bubble supplier based on a detection result of the sensor.Type: GrantFiled: December 11, 2020Date of Patent: June 13, 2023Assignee: Kioxia CorporationInventors: Shinsuke Muraki, Satoshi Nakaoka
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Patent number: 11673830Abstract: In a method for removing an organic adhesive from a glass carrier in a semiconductor manufacturing process, the glass carrier is placed into a process chamber. The glass carrier is rotated and heated sulfuric acid is applied or sprayed onto the glass carrier. Ozone is introduced into the process chamber. The ozone diffuses through the sulfuric acid to the organic adhesive on the surface of the glass carrier. The sulfuric acid and the ozone chemically react with the organic adhesive and remove it from the glass carrier.Type: GrantFiled: November 11, 2020Date of Patent: June 13, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Eric J. Bergman, David P. Surdock, Graeme Bell
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Patent number: 11670499Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: March 18, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Patent number: 11660644Abstract: A substrate processing method includes a substrate holding step of holding a substrate having a front surface on which a metal is exposed, an inert gas replacing step of replacing an atmosphere around the front surface of the substrate with an inert gas by supplying an inert gas to a vicinity of the front surface of the substrate, an adjusting step of adjusting a pH of the rinsing liquid so as to form an inactive state in which the metal does not react with the rinsing liquid or so as to form a passive state by allowing the metal to react with the rinsing liquid, and a rinsing liquid supplying step of supplying the rinsing liquid whose pH has been adjusted to the front surface of the substrate after the atmosphere around the front surface of the substrate has been replaced with the inert gas.Type: GrantFiled: April 10, 2018Date of Patent: May 30, 2023Inventors: Akihisa Iwasaki, Hiroaki Takahashi
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Patent number: 11640115Abstract: A substrate processing apparatus includes a processing chamber providing a processing space for processing a substrate and processing a substrate, a substrate support configured to support the substrate, a blocking plate below the substrate support and configured to prevent supercritical fluid from being directly sprayed onto the substrate, a first supply device configured to supply supercritical fluid under a first condition to the processing chamber, a second supply device configured to supply supercritical fluid under a second condition at a higher temperature than that of supercritical fluid under the first condition to the processing chamber, a discharge device configured to discharge supercritical fluid from the processing chamber, and a control device configured to control operations of the first supply device, the second supply device, and the discharge device. The control device is configured to direct the first supply device to supply supercritical fluid prior to the second supply device.Type: GrantFiled: September 3, 2021Date of Patent: May 2, 2023Inventors: Jihoon Jeong, Seohyun Kim, Sukhoon Kim, Younghoo Kim, Sangjine Park, Kuntack Lee
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Patent number: 11618060Abstract: An ultrasonic cleaning apparatus capable of cleaning large-sized objects includes: a casing having a bottom surface that forms a tilted surface to oppose the object to be cleaned and having an ultrasonic transducer provided at an inner lower surface; a cleaning liquid supply device configured to supply cleaning liquid to a casing bottom surface; and a flow-speed accelerator that ejects the cleaning liquid by accelerating the flow speed of the cleaning liquid from the cleaning liquid supply device. The casing is formed by a main body including an upper plate, a projected part attached to a lower part of the upper plate, an outer lateral face extended from the projected part in a downward direction, and the bottom surface connected integrally at a lower end part of the outer lateral face. The bottom surface is formed to be tilted at a prescribed angle with respect to a horizontal plane.Type: GrantFiled: August 21, 2018Date of Patent: April 4, 2023Assignee: KAIJO CORPORATIONInventors: Keisuke Ohata, Noriyuki Sakamoto
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Patent number: 11615986Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.Type: GrantFiled: September 17, 2021Date of Patent: March 28, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Xuebin Li, Wei Liu, Gaurav Thareja, Shashank Sharma, Patricia M. Liu, Schubert Chu
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Patent number: 11610773Abstract: Embodiments described herein relate to a high pressure processing system with a condenser and methods for utilizing the same. The processing system includes a process chamber, a boiler, a condenser, and one or more heat exchangers. The boiler generates a fluid, such as a vapor or supercritical fluid, and delivers the fluid to the process chamber where a substrate is processed. After processing the substrate, the system is depressurized and the fluid is delivered to the condenser where the fluid is condensed.Type: GrantFiled: March 26, 2020Date of Patent: March 21, 2023Assignee: Applied Materials, Inc.Inventor: Jean Delmas
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Patent number: 11600502Abstract: A substrate liquid processing apparatus includes a processing tub configured to store a processing liquid therein; a processing liquid supply configured to supply the processing liquid into the processing tub; a processing liquid drain device configured to drain the processing liquid from the processing tub; and a controller configured to control the processing liquid supply and the processing liquid drain device. The controller calculates, in response to an instruction to change a concentration of a preset component of the processing liquid stored in the processing tub, a drain amount and a feed amount of the processing liquid from/into the processing tub based on information upon a current concentration of the preset component, information upon a concentration increment thereof per unit time and information upon the changed concentration thereof, and controls the processing liquid supply and the processing liquid drain device based on the calculation result.Type: GrantFiled: August 21, 2019Date of Patent: March 7, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Hiroshi Yoshida, Yuki Ishii
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Patent number: 11569085Abstract: The natural oxidation film of polysilicon, which is exposed at a side surface of a recess portion 83 provided in a substrate W, is removed and a thin film 84 of polysilicon is exposed at the side surface of the recess portion 83. Liquid IPA is brought into contact with the thin film 84 of polysilicon after the natural oxidation film of polysilicon is removed. Diluted ammonia water is supplied to the substrate W and the thin film 84 of polysilicon is etched after IPA comes into contact with the thin film 84 of polysilicon.Type: GrantFiled: June 29, 2018Date of Patent: January 31, 2023Inventors: Taiki Hinode, Sadamu Fujii
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Patent number: 11538697Abstract: A substrate processing apparatus, including a processing chamber including a first internal space and a second internal space arranged in a vertical direction, the first internal space being configured to receive process gas to generate plasma; an induction electrode configured to divide the processing chamber, and having a plurality of through-holes arranged to connect the first internal space and the second internal space, wherein the plurality of through-holes are configured to induce an ion beam extracted from ions included in the plasma generated in the first internal space; a radical supply located in the second internal space, and including a reservoir configured to receive chemical liquid in which an object to be processed is immersed, and a lower electrode configured to apply nanopulses to the reservoir to generate radicals from the chemical liquid; and a chemical liquid supply configured to supply the chemical liquid to the reservoir.Type: GrantFiled: September 10, 2020Date of Patent: December 27, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Ki Nam, Jang-Yeob Lee, Sungyeol Kim, Sunghyup Kim, Soonam Park, Siqing Lu
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Patent number: 11523921Abstract: The present disclosure provides a method for producing a multifunctional implantable structure, the method having: preparing an implantable base; coating a polymer layer on the base, wherein the polymer layer is partially curable; curing the polymer layer such that the polymer layer has cured and non-cured portions; and dry-etching the polymer layer to remove the non-cured portion thereof, to allow the polymer layer to have a nano-turf structure having pores defined therein.Type: GrantFiled: April 4, 2018Date of Patent: December 13, 2022Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Tae Il Kim, So Ri Lee, Ji Yeon Lee, Gyo Yeon Hwang
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Patent number: 11476130Abstract: A substrate processing apparatus includes a liquid processing tank, a movement mechanism, an ejector, and a controller. The liquid processing tank stores a processing liquid. The movement mechanism moves a plurality of substrates immersed in the liquid processing tank to a position above the liquid surface of the processing liquid. The ejector ejects a vapor of an organic solvent toward portions of the plurality of substrates that are exposed from the liquid surface. The controller changes an ejection flow rate of the vapor ejected by the ejector as the plurality of substrates are moved up.Type: GrantFiled: March 2, 2020Date of Patent: October 18, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Kotaro Tsurusaki, Koji Yamashita, Kazuya Koyama, Kouzou Kanagawa
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Patent number: 11443963Abstract: A substrate processing method includes a process of cooling a substrate to below a freezing point of a processing liquid using a cooling fluid brought into contact with the substrate opposite. While the substrate is cooled to below the freezing point of the processing liquid, a droplet of processing liquid is dispensed onto a surface of the substrate at a specified location of a foreign substance. The droplet then forms a frozen droplet portion at the specified location. The frozen droplet portion is then thawed.Type: GrantFiled: August 30, 2019Date of Patent: September 13, 2022Assignee: KIOXIA CORPORATIONInventors: Mana Tanabe, Kosuke Takai, Kenji Masui, Kaori Umezawa
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Patent number: 11417511Abstract: A method for drying a wafer at room temperature includes a cleaning step, a reacting step and a pressure releasing step. The cleaning step includes putting a processing workpiece into a cleaning solvent. The reacting step includes putting the processing workpiece along with the cleaning solvent into a reaction chamber, implanting a supercritical fluid into the reaction chamber, and increasing a pressure of the reaction chamber to dissolve the cleaning solvent in the supercritical fluid. A critical temperature of the supercritical fluid is below room temperature. The pressure releasing step includes releasing the pressure of the reaction chamber and discharging the supercritical fluid together with the cleaning solvent out of the reaction chamber, after completely dissolving the cleaning solvent in the supercritical fluid.Type: GrantFiled: July 23, 2021Date of Patent: August 16, 2022Assignee: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Ting-Chang Chang, Chih-Cheng Yang, Wen-Chung Chen, Chuan-Wei Kuo, Pei-Yu Wu, Chun-Chu Lin
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Patent number: 11175585Abstract: An object of the present invention is to provide a treatment liquid which is capable of suppressing the generation of defects of a semiconductor device and has excellent corrosion resistance and wettability. The treatment liquid of the present invention is a treatment liquid for a semiconductor device, containing at least one organic solvent selected from the group consisting of ethers, ketones, and lactones, water, and a metal component including at least one metal element selected from the group consisting of Na, K, Ca, Fe, Cu, Mg, Mn, Li, Al, Cr, Ni, Ti, and Zn, in which the content of water in the treatment liquid is 100 ppb by mass to 100 ppm by mass and the content of the metal component in the treatment liquid is 10 ppq by mass to 10 ppb by mass.Type: GrantFiled: October 26, 2018Date of Patent: November 16, 2021Assignee: FUJIFILM CorporationInventors: Satoru Murayama, Tetsuya Shimizu, Tetsuya Kamimura
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Patent number: 10940228Abstract: Aqueous compositions, methods of manufacturing such aqueous compositions, and methods of removing reducing and/or suppressing malodours using such aqueous compositions are described. These compositions utilize a combination of hydrogen peroxide, a source of copper II, nonionic surfactant and alcohol to provide a highly effective and stable malodour removing, reducing and/or suppressing composition. The compositions are particularly useful as aerosol compositions for effective malodour removal, reduction and/or suppression in particular malodours from open sites such as landfill and in closed domestic environments such as the home. Also described is a stabilized hydrogen peroxide solution, which is stable on the addition of copper (II) salts.Type: GrantFiled: June 5, 2017Date of Patent: March 9, 2021Assignee: 2PURE PRODUCTS LIMITEDInventor: Peter Carty
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Patent number: 10685868Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.Type: GrantFiled: August 28, 2019Date of Patent: June 16, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
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Patent number: 10627161Abstract: A laboratory equipment having an inlet and outlet tube for gas to enter and exit using specific shaped tubes with multi-outlet apertures in form of a network to allow the gas to enter the drying chamber to dry the material. The specific shaped tubes are in crescent shape and cross each other to have maximum surface area exposure to the drying chamber and effectively contact the material that is being dried. A gas inlet valve and outlet valve control the flow, pressure and temperature of the gas that is being used for drying the material to make nano material. A method of using the laboratory equipment with special gas inlet tubes is used for drying the material in form a slurry to make dry nano material.Type: GrantFiled: January 24, 2018Date of Patent: April 21, 2020Assignee: KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY (KACST)Inventors: Mohammed Ahmad S. Alshamsi, Sulaiman Mohammed Alfadul
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Patent number: 10546762Abstract: Methods of drying a semiconductor substrate may include applying a drying agent to a semiconductor substrate, where the drying agent wets the semiconductor substrate. The methods may include heating a chamber housing the semiconductor substrate to a temperature above an atmospheric pressure boiling point of the drying agent until a vapor-liquid equilibrium of the drying agent within the chamber has been reached. The methods may further include venting the chamber, where the venting vaporizes the liquid phase of the drying agent from the semiconductor substrate.Type: GrantFiled: November 15, 2017Date of Patent: January 28, 2020Assignee: Applied Materials, Inc.Inventors: Eric J. Bergman, John L. Klocke, Paul McHugh, Stuart Crane, Richard W. Plavidal
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Patent number: 10541131Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.Type: GrantFiled: June 5, 2018Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
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Patent number: 10541130Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.Type: GrantFiled: June 5, 2018Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
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Patent number: 10541129Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.Type: GrantFiled: August 7, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Yun Seog Lee, Talia S. Gershon, Joel P. De Souza, Devendra K. Sadana
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Patent number: 10494715Abstract: Methods and apparatuses for removing photoresist patterning scum from patterning mandrel structures without damaging other features or structures on a semiconductor substrate are desirable for patterning precision. Methods involve cleaning carbon-containing features on a semiconductor substrate by an atomic layer cleaning (ALC) process to descum the carbon-containing features without substantially modifying feature critical dimensions. The ALC process involves exposing the carbon-containing features to an oxidant or reductant in absence of a plasma, or other energetic activation, to modify scum on the surface of the carbon-containing features. The modified scum on the surface of the carbon-containing features is then exposed to an inert gas along with a plasma ignited at a pressure between 0.1 Torr and 10 Torr and a power of less than 200 W to remove the modified scum from the surface of the carbon-containing features.Type: GrantFiled: July 19, 2017Date of Patent: December 3, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Pulkit Agarwal, Purushottam Kumar, Adrien LaVoie
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Patent number: 10283345Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: heating a substrate disposed within a processing volume of a substrate processing chamber to a temperature of up to about 400 degrees Celsius, wherein the substrate comprises a first surface, an opposing second surface, and an opening formed in the first surface and extending towards the opposing second surface, and wherein the second surface comprises a conductive material disposed in the second surface and aligned with the opening; and exposing the substrate to a process gas comprising about 80 to about 100 wt. % of an alcohol to reduce a contaminated surface of the conductive material.Type: GrantFiled: September 29, 2016Date of Patent: May 7, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Xiangjin Xie, Feng Q. Liu, Daping Yao, Alexander Jansen, Joung Joo Lee, Adolph Miller Allen, Xianmin Tang, Mei Chang
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Patent number: 10236261Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.Type: GrantFiled: April 20, 2017Date of Patent: March 19, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
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Patent number: 10236381Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.Type: GrantFiled: May 30, 2017Date of Patent: March 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
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Patent number: 10224224Abstract: A high-pressure processing system for processing a substrate includes a first chamber, a pedestal positioned within the first chamber to support the substrate, a second chamber adjacent the first chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, and a gas delivery system configured to introduce a processing gas into the first chamber and to increase the pressure within the first chamber to at least 10 atmospheres while the processing gas is in the first chamber and while the first chamber is isolated from the second chamber.Type: GrantFiled: December 7, 2017Date of Patent: March 5, 2019Assignee: Micromaterials, LLCInventors: Qiwei Liang, Srinivas D. Nemani, Adib Khan, Venkata Ravishankar Kasibhotla, Sultan Malik, Sean S. Kang, Keith Tatseun Wong
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Patent number: 10204793Abstract: A chemical mechanical polishing (CMP) slurry, a method for CMP, and a manufacturing method of a semiconductor structure are provided. The CMP slurry includes a pH-adjustor for providing an alkaline environment in the CMP slurry and a silicon inhibitor for lowering a removal rate of silicon. The CMP slurry is used in a planarization operation to remove portions of a semiconductor region and portions of a silicon region. The semiconductor region comprises at least one semiconductor material different from silicon. The semiconductor region is formed in a recess adjacent to the silicon region. The particle defect condition may be improved by applying the alkaline CMP slurry, and the silicon inhibitor may be used to modify the removal rate selectivity between the semiconductor region and the silicon region in the planarization operation.Type: GrantFiled: May 17, 2016Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Shu-Hao Huang
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Patent number: 9859162Abstract: A method for separation of semiconductor device cell units from fabricated large-area cell units, together with a corresponding tile unit structure, are provided in which the tile unit is cut along cell unit boundaries while leaving intact a set of specified tab sections distributed along the cell unit boundaries. The tile unit may be a multi-layer composite of a semiconductor layer with a conductive metallic base supported upon a polymer layer and adhered thereto by an adhesive film, wherein tab sections are cut completely through the semiconductor layer and its metallic base from above and may also be cut partially through the polymer layer from below, leaving at least a portion of the polymer layer in place at tab sections. Tile units can be handled such that component cell units are held together by the tab sections, until a physical final separation of selected cell units.Type: GrantFiled: March 20, 2015Date of Patent: January 2, 2018Assignee: ALTA DEVICES, INC.Inventors: Khurshed Sorabji, Daniel G. Patterson
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Patent number: 9831081Abstract: In embodiment, the method includes cleaning a preceding substrate, and drying the preceding substrate and cleaning a next substrate. Drying the preceding substrate and cleaning the next substrate include determining a cleaning start time of the next substrate, and the cleaning start time corresponds to a desired time point after starting drying the preceding substrate.Type: GrantFiled: June 8, 2016Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jihoon Jeong, Jung-Min Oh, Kuntack Lee, Hyosan Lee
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Patent number: 9761749Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.Type: GrantFiled: February 20, 2015Date of Patent: September 12, 2017Assignee: Semiconductor Energy Laboratory Co., LTD.Inventors: Takashi Hirose, Naoto Kusumoto
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Patent number: 9728621Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.Type: GrantFiled: September 28, 2016Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
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Patent number: 9522844Abstract: A low temperature poly-silicon thin film preparation apparatus and a method for preparing the same are disclosed, the preparation apparatus comprises a substrate cleaning tank and an ozone generating device connected thereto, such that not only can blow off residual liquid on a surface of a glass substrate, but can also allow the glass substrate to directly contact the ozone, such that a silicon film on the surface of the glass substrate is more smooth and less impure, and an oxide film formed on the surface is more uniform since it contacts with the ozone at the first time after being cleaned by hydrofluoric acid, therefore the crystalline effect is more excellent.Type: GrantFiled: September 23, 2014Date of Patent: December 20, 2016Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Jia Li
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Patent number: 8956884Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.Type: GrantFiled: January 26, 2011Date of Patent: February 17, 2015Assignee: DunAn Microstaq, Inc.Inventor: Parthiban Arunasalam
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Patent number: 8815017Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.Type: GrantFiled: July 26, 2013Date of Patent: August 26, 2014Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Masayuki Takeda, Norikazu Nakamura, Junichi Kon
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Patent number: 8722545Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.Type: GrantFiled: August 27, 2012Date of Patent: May 13, 2014Assignee: STMicroelectronics Pte Ltd.Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
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Patent number: 8716149Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.Type: GrantFiled: May 29, 2012Date of Patent: May 6, 2014Assignee: GlobalFoundries, Inc.Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
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Patent number: 8703605Abstract: A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated.Type: GrantFiled: July 7, 2010Date of Patent: April 22, 2014Inventor: Byung Chun Yang