Etching Insulating Layer By Chemical Or Physical Means (epo) Patents (Class 257/E21.249)
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Publication number: 20130052785Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening having open end shape in which open end length is elongated compared with an opening having linear open end shape.Type: ApplicationFiled: October 28, 2011Publication date: February 28, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Tatsuya MASHIKO, Shigeru SUGIOKA, Nobuyuki SAKO, Ryoichi TANABE
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Patent number: 8383518Abstract: A method for forming contact holes is applied in a transistor array substrate. The transistor array substrate includes first contact pads, second contact pads located over the first contact pads, a first insulation layer covering the first contact pads, and a second insulation layer covering the second contact pads. Firstly, a photoresist pattern layer having recesses and first openings is formed on the second insulation layer. The first openings expose the second insulation layer partially. Then, the first insulation layer and the second insulation layer inside the first openings are removed partially, to expose the first contact pads. Then, the thickness of the photoresist pattern layer is reduced, so that the recesses form a plurality of second openings which expose the second insulation layer partially. After that, a part of the second insulation layer which is located inside the second openings is removed, to expose the second contact pads.Type: GrantFiled: December 14, 2011Date of Patent: February 26, 2013Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Wen-Cheng Lu, Yang-Yu Yao
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Publication number: 20130045591Abstract: A method of semiconductor processing includes coating a top surface of a substrate having a semiconductor surface with a positive photoresist layer. The positive photoresist layer is exposed using a reticle or a mask that defines a pattern. The positive photoresist layer is doped by introducing at least one material modifying species after exposing. The positive photoresist layer is developed with a negative tone developer to form a patterned positive photoresist layer which provides masked portions of the top surface and unmasked portions of the top surface. A selective process is then performed to the unmasked portions of the top surface.Type: ApplicationFiled: August 15, 2012Publication date: February 21, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: JUDY BROWDER SHAW, SCOTT WILLIAM JESSEN
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Publication number: 20130040463Abstract: A mask layer is formed by: a step in which a first photoresist layer is formed, exposed, and developed on a substrate, thereby forming a first photoresist pattern; a step in which the first photoresist pattern is made insoluble; a step in which a second photoresist layer is formed, exposed, and developed on top of the first photoresist layer, thereby forming a second photoresist pattern that intersects the first photoresist pattern; a step in which the second photoresist pattern is made insoluble; and a step in which a third photoresist layer is formed, exposed, and developed on top of the first and second photoresist patterns, thereby forming a third photoresist pattern.Type: ApplicationFiled: February 17, 2011Publication date: February 14, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: Kenichi Oyama
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Publication number: 20130040452Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.Type: ApplicationFiled: October 16, 2012Publication date: February 14, 2013Inventor: Samsung Electronics Co., Ltd.
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Publication number: 20130037879Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: Micron Technology, Inc.Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
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Publication number: 20130020682Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
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Publication number: 20130023081Abstract: A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.Type: ApplicationFiled: July 20, 2011Publication date: January 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jia LIN, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang
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Publication number: 20130017682Abstract: In one exemplary embodiment of the invention, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer; after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores, where heating the structure results in residual filling material being left on the surface of the first layer; and after heating the structure, removing the residual filling material by applying a solvent wash.Type: ApplicationFiled: July 12, 2011Publication date: January 17, 2013Applicant: International Business Machines CorporationInventors: Robert L. Bruce, Geraud Jean-Michel Dubois, Theo J. Frot, Willi Volksen
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Publication number: 20130009283Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: MICRON TECHNOLOGY, INC.Inventor: Baosuo Zhou
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Publication number: 20120326766Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, JR., Ephrem G. Gebreselasie, Richard A. Phelps, Yun Shi, Andreas D. Stricker
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Publication number: 20120329281Abstract: A shape defect in a transfer pattern formed over the major surface of a substrate is prevented by using an immersion exposure method. When exposure light is radiated onto a resist, immersion water is held in a first immersion area between each of the lower surfaces of an optical element of a projection optical system and a nozzle portion, and a resist; and when a focus, optical system alignment, or the like, is regulated, the immersion water is held in a second immersion area between each of the lower surfaces of the optical element of the projection optical system and the nozzle portion, and the upper surface of a measurement stage. A transverse spread of the immersion water held in the first immersion area is made smaller than that of the immersion water held in the second immersion area.Type: ApplicationFiled: June 16, 2012Publication date: December 27, 2012Inventor: Shuichi YAMAYA
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Patent number: 8338282Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap and forming a cavity in which the micro component is positioned, depositing, at least on the cap, at least one layer of plugging material that plugs the at least one opening, and performing a localized deposition of at least one portion of mechanically reinforcing material of the cap, covering at least the cap, wherein the mechanically reinforcing material is not subsequently etched.Type: GrantFiled: February 2, 2011Date of Patent: December 25, 2012Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Jean-Louis Pornin, Charlotte Gillot
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Publication number: 20120322259Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Inventor: Kun-Yi Liu
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Publication number: 20120322246Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung WANG, Hsien-Chin LIN, Yuan-Ching PENG, Chia-Pin LIN, Fan-Yi HSU, Ya-Jou HSIEH
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Publication number: 20120322253Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.Type: ApplicationFiled: August 27, 2012Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Liang-Gi YAO, Chun-Hu CHENG, Chen-Yi LEE, Jeff J. XU, Clement Hsingjen WANN
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Publication number: 20120315765Abstract: There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hardmask. A resist underlayer film forming composition for lithography, includes as a silane compound, a hydrolyzable organosilane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein the hydrolyzable organosilane is a hydrolyzable organosilane of Formula (1): R1aR2bSi(R3)4?(a+b)??Formula (1) wherein R1 is Formula (2): in which R4 is an organic group, and R5 is a C1-10 alkylene group, a hydroxyalkylene group, a sulfide bond, an ether bond, an ester bond, or a combination thereof, X1 is Formula (3), Formula (4), or Formula (5): R2 is an organic group, and R3 is a hydrolysable group.Type: ApplicationFiled: February 18, 2011Publication date: December 13, 2012Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Makoto Nakajima, Yuta Kanno, Wataru Shibayama
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Publication number: 20120309199Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.Type: ApplicationFiled: August 26, 2011Publication date: December 6, 2012Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
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Publication number: 20120302066Abstract: A method of manufacturing a semiconductor device, which includes forming a resist layer on a substrate, performing an exposure and development process on the resist layer to form a resist pattern, performing a slimming process to slim the resist pattern, forming a mask material layer on side walls of the slimmed resist pattern, and removing the slimmed resist pattern. The slimming process further includes coating an extensive agent on the substrate, expanding the expansive agent, and removing the expanded expansive agent.Type: ApplicationFiled: May 6, 2011Publication date: November 29, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Fumiko Iwao
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Publication number: 20120299160Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Peter Baars, Marco Lepper, Thilo Scheiper
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Publication number: 20120301981Abstract: The present invention is directed to a method for the fabrication of electron field emitter devices, including carbon nanotube (CNT) field emission devices. The method of the present invention involves depositing one or more electrically conductive thin-film layers onto a electrically conductive substrate and performing lithography and etching on these thin film layers to pattern them into the desired shapes. The top-most layer may be of a material type that acts as a catalyst for the growth of single- or multiple-walled carbon nanotubes (CNTs). Subsequently, the substrate is etched to form a high-aspect ratio post or pillar structure onto which the previously patterned thin film layers are positioned. Carbon nanotubes may be grown on the catalyst material layer. The present invention also described methods by which the individual field emission devices may be singulated into individual die from a substrate.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Inventors: Mehmet OZGUR, Paul SUNAL, Lance OH, Michael HUFF, Michael PEDERSEN
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Patent number: 8318540Abstract: A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.Type: GrantFiled: May 19, 2008Date of Patent: November 27, 2012Assignee: Infineon Technologies AGInventor: Gottfried Beer
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Publication number: 20120282778Abstract: A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Inventors: Scott L. Light, Anton J. deVilliers
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Publication number: 20120282776Abstract: A photoresist underlayer composition includes a solvent, and a polysiloxane resin represented by Chemical Formula 1: {(SiO1.5—Y—SiO1.5)(SiO2)y(XSiO1.5)z}(OH)e(OR1)f.Type: ApplicationFiled: July 2, 2012Publication date: November 8, 2012Inventors: Mi-Young KIM, Sang-Kyun KIM, Hyeon-Mo CHO, Chang-Soo WOO, Sang-Ran KOH, Hui-Chan YUN, Woo-Jin LEE, Jong-Seob KIM
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Publication number: 20120273821Abstract: A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns.Type: ApplicationFiled: April 18, 2012Publication date: November 1, 2012Applicant: SINO-AMERICAN SILICON PRODCUTS INC.Inventors: Cheng-Hung Wei, Bo-Wen Lin, Ching-Yen Peng, Hao-Chung Kuo, Wen-Ching Hsu
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Publication number: 20120276745Abstract: A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern.Type: ApplicationFiled: December 20, 2011Publication date: November 1, 2012Inventors: Jin-Ki JUNG, Jung-Hee Park
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Patent number: 8298961Abstract: A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.Type: GrantFiled: December 30, 2009Date of Patent: October 30, 2012Assignee: Hynix Semiconductor Inc.Inventor: Sung Kee Park
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Publication number: 20120270402Abstract: A method of making an array columnar hollow semiconductor structure includes: providing an oxide layer; placing a chromeless mask on the oxide layer, wherein the chromeless mask is a bank-shaped frame; forming a silicone nitride layer to cover the first partial top surface of the oxide layer and the whole outer surface of the bank-shaped frame; removing one part of the silicone nitride layer to expose a second partial top surface of the oxide layer and a top surface of the bank-shaped frame; removing the bank-shaped frame to expose a third partial top surface of the oxide layer; removing a first part of the oxide layer under the second partial top surface and a second portion of the oxide layer under the third partial top surface to form a plurality of columnar hollow bodies; and removing the other silicone nitride layer to completely expose the columnar hollow bodies.Type: ApplicationFiled: May 20, 2011Publication date: October 25, 2012Applicant: INOTERA MEMORIES, INC.Inventor: TAH-TE SHIH
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Publication number: 20120264305Abstract: A method of forming side spacers upwardly extending from a substrate, includes: providing a template constituted by a photoresist formed on and in contact with an etch-selective layer laminated on a substrate; anisotropically etching the template in a thickness direction with an oxygen-containing plasma to remove a footing of the photoresist and an exposed portion of the underlying layer; depositing a spacer film on the template by atomic layer deposition (ALD); and forming side spacers using the spacer film by etching. The etch-selective layer has a substantially lower etch rate than that of the photoresist.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Applicant: ASM JAPAN K.K.Inventor: Ryu Nakano
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Patent number: 8288292Abstract: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower than silicon nitride.Type: GrantFiled: March 30, 2010Date of Patent: October 16, 2012Assignee: Novellus Systems, Inc.Inventors: George Andrew Antonelli, Mandyam Sriram, Vishwanathan Rangarajan, Pramod Subramonium
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Patent number: 8288242Abstract: Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.Type: GrantFiled: August 16, 2011Date of Patent: October 16, 2012Assignee: Hynix Semiconductor Inc.Inventors: Byeong Ho Cho, Sung Woo Ko
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Publication number: 20120248460Abstract: Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to light and/or heat. The freestanding film is then exposed to a laser beam in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.Type: ApplicationFiled: August 2, 2011Publication date: October 4, 2012Inventors: Margaret H. ABRAHAM, David P. Taylor
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Patent number: 8278208Abstract: A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug.Type: GrantFiled: January 12, 2012Date of Patent: October 2, 2012Assignee: Hynix Semiconductor Inc.Inventor: Hee Jung Yang
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Publication number: 20120244713Abstract: A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier.Type: ApplicationFiled: December 23, 2011Publication date: September 27, 2012Inventor: Sung Koo LEE
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Publication number: 20120244707Abstract: In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.Type: ApplicationFiled: September 21, 2011Publication date: September 27, 2012Inventors: Taiga Uno, Toshiya Kotani, Hiromitsu Mashita, Yukiyasu Arisawa
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Publication number: 20120241914Abstract: A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.Type: ApplicationFiled: September 4, 2009Publication date: September 27, 2012Applicant: X-Fab Semiconductor Foundries AGInventors: Hyung Sun Yook, Tsui Ping Chu, Poh Ching Sim
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Publication number: 20120240674Abstract: In a thermal sensor with a detection part and a circuit part formed on the same substrate, an insulating film for protection of the circuit part causes problems of lowering in sensitivity of a heater, deterioration in accuracy due to variation of a residual stress in the detection part, etc. A layered film including insulating films is formed on a heating resistor, an intermediate layer is formed thereon, and a layered film including insulating films is formed further thereon. The intermediate layer is specified to be a layer made up of any one of aluminum nitride, aluminum oxide, silicon carbide, titanium nitride, tungsten nitride, and titanium tungsten. This configuration enables the layered film on the upper part of the detection part to be removed using the intermediate layer as an etch stop layer, which solves problems of lowering in sensitivity, a variation in residual stress, etc. resulting from these.Type: ApplicationFiled: January 16, 2012Publication date: September 27, 2012Inventor: Noriyuki SAKUMA
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Publication number: 20120243095Abstract: The invention relates to a micromechanical unit, in particular, an adjustable optical filter, and also a method to manufacture the unit. The unit comprises a first device layer and a second substrate layer at least partially fastened to each other, where the device layer comprises a number of reflecting elements divided between a number of non movable, fixed reflecting elements, where the fixed elements are connected with the substrate, and where a cavity is defined between the substrate and each movable element and each movable element is set up to produce a spring-loaded movement into the cavity, and where a number of dielectric spacer blocks are placed in the cavities between each movable element and the substrate to avoid electric contact between them.Type: ApplicationFiled: August 13, 2010Publication date: September 27, 2012Inventors: Hakon Sagberg, Ib-Rune Johansen, Sigurd Teodor Moe, Matthieu Lacolle, Thor Bakke, Dag Thorstein Wang, Elisabeth Larsen Rogne, Henrik Rogne
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Publication number: 20120238099Abstract: According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed.Type: ApplicationFiled: September 18, 2011Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi SHUNDO, Fumiki Aiso
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Publication number: 20120238097Abstract: Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.Type: ApplicationFiled: September 29, 2011Publication date: September 20, 2012Inventors: Ru Huang, Shuangshuang Pu, Yujie Ai, Zhihua Hao, Runsheng Wang
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Publication number: 20120228703Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, and an insulating member. The semiconductor substrate has a trench formed in a top surface. The insulating member is provided in the trench. A space is formed between the semiconductor substrate and the insulating member.Type: ApplicationFiled: September 21, 2011Publication date: September 13, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Koichi YAMAOKA
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Publication number: 20120231553Abstract: A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a first processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoichi OKITA, Koji IBI, Minoru Suzuki, Yuuichi Tachino
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Publication number: 20120225557Abstract: Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from ?80 degrees Celsius to ?140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.Type: ApplicationFiled: March 1, 2012Publication date: September 6, 2012Applicants: THE AMERICAN UNIVERSITY IN CAIRO, KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Mohamed Serry, Andrew Rubin, Mohamed Refaat, Sherif Sedky, Mohammad Abdo
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Publication number: 20120225558Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Applicant: APPLIED MATERIALS, INCInventors: MEI CHANG, Linh Thanh, Bo Zheng, Arvind Sundarrajan, John C. Forster, Umesh M. Kellkar, Murali Narasimhan
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Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20120220130Abstract: A method for fabricating a semiconductor device includes forming a trench over a substrate, forming a spin on dielectric (SOD) layer in a first part of the trench, and forming an oxide layer within the trench, where the oxide layer is formed over the SOD layer by using a process for plasma chemical vapor deposition.Type: ApplicationFiled: December 27, 2011Publication date: August 30, 2012Inventor: Chai-O CHUNG
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Publication number: 20120220131Abstract: A method for fabricating a semiconductor memory device includes forming a photoresist layer on a substrate, performing an exposure process such by illuminating a first area of the photoresist layer with a first amount of a light and illuminating a second area of the photoresist layer with a light of a second amount smaller than the first amount, removing the first area of the photoresist layer to form a photoresist pattern, and forming a capping layer on a surface of the photoresist pattern.Type: ApplicationFiled: December 21, 2011Publication date: August 30, 2012Inventor: Tae-Seung EOM
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Publication number: 20120220124Abstract: A method for fabricating a semiconductor device includes forming an insulation layer containing an impurity, forming a contact hole by etching the insulation layer, performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer, and rinsing the contact hole.Type: ApplicationFiled: September 22, 2011Publication date: August 30, 2012Inventors: Soo-Byung Ko, Kee-Joon Oh, Sung-Hyun Yoon, Soon-Young Park
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Publication number: 20120214310Abstract: A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Ben-Li Sheu, Rajinder Dhindsa, Vinay Pohray, Eric A. Husdon, Andrew D. Bailey, III
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Publication number: 20120208364Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.Type: ApplicationFiled: June 16, 2011Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyong Bong ROUH, Yong Seok EUN, Eun Shil PARK