Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Abstract: In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through the via hole resist mask. Then, the via hole resist mask is removed by an ashing process and a protective film is formed on an underlayer of the insulating film; Thereafter, a trench is formed by etching the insulating film through the trench mask, and the semiconductor substrate is unloaded from the processing chamber after the via hole forming step, the resist mask removing step, the protective film forming step and the trench forming step are completed in the processing chamber.

Abstract: A method for forming a gate electrode of a semiconductor device is provided wherein a hard mask layer which is a nitride film is deposited and subjected to an additional surface deposition process so that a matrix structure of a nitride film surface becomes more compact to reduce an etching ratio of the hard mask layer thereby increasing a thickness of the residual hard mask layer.

Abstract: A semiconductor device manufacturing method using a KrF light source is disclosed. Embodiments relate to a method for manufacturing a semiconductor device including forming an oxide film over a semiconductor substrate. A gate conductor may be formed over the oxide film. An antireflective film may be formed over the gate conductor. A photoresist film may be formed over the antireflective film. The photoresist film may be photo-etched, thereby forming a first photoresist film pattern having a first line width. The antireflective film may be etched, using the first photoresist film pattern as a mask, thereby forming an antireflective film pattern. The first photoresist film pattern may be simultaneously laterally etched, thereby forming a second photoresist film pattern having a second line width corresponding to a final design value for the gate conductor.

Abstract: The present invention is a method of etching a lower layer film (64) of an organic material formed on a surface layer (61) of a substrate, using an upper layer film (63) of an Si-containing organic material as a mask. A mixed gas containing an NH3 gas and an O2 gas is supplied into the processing vessel as an etching gas, so as to perform etching by a plasma of the etching gas. When the etching gas is supplied into the processing vessel, a CD shift value of etching can be controlled by adjusting a flow ratio of O2 gas to the NH3 gas. Specifically, a satisfactory CD shift value can be obtained when the flow ratio is from 0.5 to 20%, and preferably, 5 to 10%.

Abstract: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist on an entire surface of the semiconductor substrate such that the via hole and the trench may be filled thereby; removing a polymer defect in the trench while removing the coated photoresist by a plasma treatment under predetermined process conditions; and performing a wet cleaning process so as to remove a residue of the photoresist.

Abstract: A cleaning arrangement for a lithographic apparatus module may be provided in a collector. The cleaning arrangement includes a hydrogen radical source configured to provide a hydrogen radical containing gas to at least part of the module and a pump configured to pump gas through the module such that a flow speed of the hydrogen radical containing gas provided through at least part of the module is at least 1 m/s. The cleaning arrangement may also include a gas shutter configured to modulate a flow of the hydrogen radical containing gas to at least part of the module, a buffer volume of at least 1 m3 in communication with the module, and a pump configured to provide a gas pressure in the buffer volume between 0.001 mbar (0.1 Pa) and 1 mbar (100 Pa). The cleaning arrangement may further include a gas return system.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.

Abstract: Plasma is generated using elemental hydrogen, a weak oxidizing agent, and a fluorine containing gas. An inert gas is introduced to the plasma downstream of the plasma source and upstream of a showerhead that directs gas mixture into the reaction chamber where the mixture reacts with the high-dose implant resist. The process removes both the crust and bulk resist layers at a high strip rate, and leaves the work piece surface substantially residue free with low silicon loss.

Abstract: A cleaning arrangement for a lithographic apparatus module may be provided in a collector. The cleaning arrangement includes a hydrogen radical source configured to provide a hydrogen radical containing gas to at least part of the module and a pump configured to pump gas through the module such that a flow speed of the hydrogen radical containing gas provided through at least part of the module is at least 1 m/s. The cleaning arrangement may also include a gas shutter configured to modulate a flow of the hydrogen radical containing gas to at least part of the module, a buffer volume of at least 1 m3 in communication with the module, and a pump configured to provide a gas pressure in the buffer volume between 0.001 mbar (0.1 Pa) and 1 mbar (100 Pa).

Abstract: A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating film is 100 or more, to an interlayer film for forming the contact plugs therein. The method comprises forming wiring lines each of which is covered with silicon oxide films at its top surface and lateral sides, forming a sacrificial interlayer film overall, which is made up of an organic coating film without containing silicon, so as to cover the wiring lines, forming contact holes by sequentially etching the sacrificial interlayer film and a lower-layer insulating film, and forming contact plugs.

Abstract: A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge roughness (LER) of the masking structure, and etching a pattern of the layered masking structure into one or more of the number of layers of the substrate assembly before trimming the layered masking structure.

Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.

Abstract: An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor substrate is selectively etched on the insulating layer side to a region at a greater depth than the embrittled layer; and the semiconductor substrate and a substrate having an insulating surface are superposed on each other and bonded to each other with the insulating layer interposed therebetween. The semiconductor substrate is heated to be separated at the embrittled layer while a semiconductor layer is left remaining over the substrate having an insulating surface.

Abstract: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such that the photoresist will protect the released structures free from the chipping, vibrations, and damages in the diamond blade dicing process. In another method, a laser dicing system is utilized to scribe the multi-project wafer placed on a platform, and by precisely controlling the platform moving-track, the dicing path can be programmed to any required shape and region, even it is not straight. In addition, the wafer backside is mounted on a blue-tape at the beginning to enhance the process reliability.

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification of the etch behavior of the exposed portion of the contact etch stop layer.

Abstract: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface of the wafer. Subsequently, the coating material layer positioned in the bevel region is removed according to the reference pattern.

Abstract: By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving a hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluorocarbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. A chamber pressure less than 20 mTorr is utilized in the second cleaning step. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.

Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

Abstract: A method for preparing an organic electronic or optoelectronic device is described. The method comprises depositing a layer of fluorinated polymer on a substrate, patterning the layer of fluorinated polymer to form a relief pattern and depositing from solution a layer of organic semiconductive or conductive material on the substrate. The fluorinated polymer may be a fluorinated photoresist and may be treated by exposure to ultraviolet light and ozone prior to the deposition of the layer of organic semiconductive or conductive material. The method has particular application in the preparation of organic light emitting devices by ink-jet printing.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: A method is provided for forming polymer on an interior surface of a reaction chamber. A polymer-forming gas is introduced into the chamber during the etching of a photoresist layer of a semiconductor wafer within the reaction chamber and the environment is regulated to form the polymer on the interior surface of the chamber. The polymer thus formed reduces the standard deviation of the critical dimensions of the semiconductor wafer. A method for the manufacture of integrated circuits is also provided.

Abstract: A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist layer on the sacrificial material to define a trench for the semiconductor device, removing the first photoresist layer without affecting the sacrificial material, repatterning a second photoresist layer on the sacrificial material to define the trench for the semiconductor device, forming the trench, and removing the second photoresist layer and the sacrificial material completely after the trench is formed.

Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.

Abstract: A dry etching method involves plasma etching an organic anti-reflecting coating film through a mask layer made of photoresist and having a predetermined pattern by using an etching gas of CF4 and O2. The method allows an organic anti-reflecting coating film to be etched such that the etched film exhibits a side wall portion having a better shape as compared with that formed by a conventional technique.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.