Abstract: Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: In certain examples, methods and semiconductor structures are directed to multilayered structures including TMD (transition metal dichalcogenide material or TMD-like material and a polymer-based layer which is characterized as exhibiting flexibility. A first layer including a TMD-based material (e.g., an atomic-thick layer including TMD) or TMD-like material is provided or grown on a surface which in certain instances may be a rigid platform or substrate. A plurality of electrodes are provided on or as part of the first layer, and another layer or film including polymer is applied to cover the first layer and the electrodes. The other layer is integrated with the TMD material or TMD-like material and the first layer, and the other layer provides a flexible substrate such as when released from the exemplary rigid platform or substrate.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.

Abstract: A combination of a chemical vapour deposition (CVD) coater and at least one capacitive proximity sensor, comprising: a CVD coater, and at least one capacitive proximity sensor attached to the CVD coater, wherein the at least one capacitive proximity sensor is arranged to determine the distance between a glass substrate and the CVD coater.

Abstract: This application relates to a method of filling a gap in a three-dimensional structure over a semiconductor substrate. The method may include depositing a thin film at least on a three-dimensional structure over a substrate using at least one reaction gas activated with a first radio frequency (RF) power having a first frequency, the three dimensional structure comprising a trench and/or hole. The method may also include etching the deposited thin film using at least one etchant activated with a second RF power having a second frequency lower than the first frequency. The method may further include repeating a cycle of the depositing and the etching at least once until the trench and/or hole are filled with the thin film. According to some embodiments, a thin film having substantially free of voids and/or seams can be formed in the three-dimensional structure.

Abstract: There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.

Abstract: An embodiment semiconductor optical device includes an optical waveguide including a core, and an active layer extending in the waveguide direction of the optical waveguide for a predetermined distance and arranged in a state in which the active layer can be optically coupled to the core. The core and the active layer are arranged in contact with each other. The core is formed of a material with a refractive index of about 1.5 to 2.2, such as SiN, for example. In addition, the core is formed to a thickness at which a higher-order mode appears. The higher-order mode is an E12 mode, for example.

Abstract: Embodiments of the disclosure provide a method to form an air gap structure. An opening is formed in a first dielectric layer between adjacent conductors. A first dielectric layer is formed over the opening to fill a first portion of the opening. A remainder of the opening is free of the first dielectric layer. A second dielectric layer is formed on a top surface of the first dielectric layer, with a remainder of the opening unfilled. The second dielectric layer is devoid of wiring. The remainder of the opening below the second dielectric layer defines an air gap structure. A wiring layer is formed above the air gap structure.

Abstract: Exemplary deposition methods may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. The method may include striking a plasma in the processing region between a faceplate and a pedestal of the semiconductor processing chamber. The pedestal may support a substrate including a patterned photoresist. The method may include maintaining a temperature of the substrate less than or about 200° C. The method may also include depositing a silicon-containing film along the patterned photoresist.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.

Abstract: The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.

Abstract: In accordance with an exemplary embodiment, a substrate processing apparatus includes: a tube assembly having an inner space in which substrates are processed and assembled by laminating a plurality of laminates, a substrate holder configured to support the plurality of substrates in a multistage manner in the inner space of the tube assembly, a gas supply unit installed on one side of the tube assembly to supply a process gas to each of the plurality of substrates in the inner space; and an exhaust unit connected to the tube assembly to exhaust the process gas supplied into the inner space, the substrate processing apparatus that induces a laminar flow to supply a uniform amount of process gas to a top surface of the substrate.

Abstract: A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

Abstract: A substrate processing apparatus includes: a mounting stand provided with a substrate mounting region in which a workpiece substrate is mounted; a process vessel for defining a process chamber including a first region and a second region through which the substrate mounting region passes in order; a precursor gas supply unit for supplying a precursor gas to the first region; a process gas supply unit for supplying a first gas or a second gas differing from the first gas to the second region; at least one plasma generating unit for generating plasma of the first gas or the second gas in the second region; and a control unit for executing a repetition control of repeating a first operation for supplying the first gas to the second region for a first time and a second operation for supplying the second gas to the second region for a second time.

Abstract: A poly(ester-carbonate) copolymer comprises carbonate units of the formula (I); and ester units of the formula (II) wherein: T is a C2-20 alkylene, a C6-20 cycloalkylene, or a C6-20 arylene; and R1 and J are each independently a bisphenol A divalent group and a phthalimidine divalent group, provided that the phthalimidine divalent group is present in an amount of 40 to 50 mol % based on the total moles of the bisphenol A divalent groups and the C 1/2 divalent group, and the ester units are present in an amount of 40 to 60 mol % based on the sum of the moles of the carbonate units and the ester units; and wherein the poly(ester-carbonate) copolymer has a weight average molecular weight of 18,000 to 24,000 Daltons; and the composition has a Tg of 210 to 235° C. and a melt viscosity of less than 1050 Pa-s at 644 sec?1 and 350° C.

Abstract: Embodiments of the invention provide a method for in-situ selective deposition and etching for advanced patterning applications. According to one embodiment the method includes providing in a process chamber a substrate having a metal-containing layer thereon, and exposing the substrate to a gas pulse sequence to etch the metal-containing layer in the absence of a plasma, where the gas pulse sequence includes, in any order, exposing the substrate to a first reactant gas containing a halogen-containing gas, and exposing the substrate to a second reactant gas containing an aluminum alkyl. According to another embodiment, the substrate has an exposed first material layer and an exposed second material layer, and the exposing to the gas pulse sequence selectively deposits an additional material layer on the exposed first material layer but not on the exposed second material layer.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

Abstract: Disclosed herein are containing silicon-based films and compositions and methods for forming the same. The silicon-based films contain <50 atomic % of silicon. In one aspect, the silicon-based films have a composition SixCyNz wherein x is about 0 to about 55, y is about 35 to about 100, and z is about 0 to about 50 atomic weight (wt.) percent (%) as measured by XPS. In another aspect, the silicon-based films were deposited using at least one organosilicon precursor comprising two silicon atoms, at least one Si-Me group, and an ethylene or propylene linkage between the silicon atoms such as 1,4-disilapentane.

Abstract: An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.

Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.

Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.

Abstract: Methods for producing coatings on substrates are provided. These methods comprise the steps of introducing the substrate in a photo-initiated chemical vapor deposition reactor, introducing a gas precursor in the reactor, irradiating said gas precursor with UV radiation at a given wavelength, thereby at least partly photodissociating the gas precursor, until the coating is formed. In one method, the gas precursor is a mixture comprising carbon monoxide and hydrogen. In another method, the pressure in the react or is between about 0.75 and 1.25 atm and the gas precursor has an absorption cross section of about 5×10?16 cm2/molecule or less at said given wavelength. In another aspect, the substrate is ash.

Abstract: Methods and apparatuses for depositing films in high aspect ratio features and trenches on substrates using atomic layer deposition and deposition of a sacrificial layer during atomic layer deposition are provided. Sacrificial layers are materials deposited at or near the top of features and trenches prior to exposing the substrate to a deposition precursor such that adsorbed precursor on the sacrificial layer is removed in an etching operation for etching the sacrificial layer prior to exposing the substrate to a second reactant and a plasma to form a film.

Abstract: A method may include generating a plasma in a plasma chamber and directing the ions comprising at least one of a condensing species and inert gas species from the plasma to a cavity within a substrate at a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The method may further include; depositing a fill material within the cavity using the condensing species, the depositing taking place concurrently with the directing the ions, wherein the fill material accumulates on a lower surface of the cavity at a first rate, and wherein the fill material accumulates on an upper portion of a sidewall of the cavity at a second rate less than the first rate.

Abstract: A heating method includes an oxide film forming step and a heating step. The thickness of an oxide film is set in a first range that includes a first maximal thickness and a second maximal thickness and that is smaller than a second minimal thickness in the relationship with the laser absorption having a periodic profile. The first maximal thickness corresponds to a first maximal value a of the laser absorption. The second maximal thickness corresponds to a second maximal value of the laser absorption. The second minimal thickness corresponds to a second minimal value of the laser absorption, namely the minimal value of the laser absorption that appears between the second maximal value and a third maximal value, or the maximal value of the laser absorption that appears subsequent to the second maximal value.

Abstract: Disclosed are a large-scale composite synthesis system, a reactor therefor, and a synthesis method using the same, wherein two or more different samples are vaporized in respective vaporizers, and are then fed into a reactor that has a relatively large transverse cross-sectional diameter compared to the connector for transporting the samples in a gas phase and is maintained at a temperature lower than that of the connector, thus producing a powder composite, the composite being synthesized while being electrostatically attached to an adherend surface.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.

Abstract: A method of fabricating a fin field effect transistor (FinFET) is provided as follows. A fin structure is formed on a substrate. A gate pattern and a source/drain (S/D) electrode are formed on the fin structure. The gate pattern and the S/D electrode are spaced apart from each other. A blocking layer is on the fin structure to cover the gate pattern and the S/D electrode. A sacrificial pattern is formed on the blocking layer and between the gate pattern and S/D electrode. The sacrificial pattern has a first thickness and a first width. A capping layer is formed on the sacrificial layer. An air gap is formed by removing the sacrificial layer through the capping layer. The air gap is formed between the gate pattern and the S/D electrode and has the first thickness and the first width.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° C. to about 150° C. such that the preliminary filling insulation layer is transformed into a filling insulation layer including polysiloxane and forming an isolation layer by planarizing the filling insulation layer.

Abstract: A semiconductor device manufacturing method of the present invention includes forming a base film having a water-repellent surface on a substrate; forming a photosensitive film having a water-repellent surface on the base film; developing the photosensitive film to expose the base film, thereby forming a photosensitive film pattern; supplying a first spacer material on the photosensitive film and on the exposed base film; and removing at least a part of the first spacer material formed on a top surface of the photosensitive film and a top surface of the base film.

Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.

Abstract: A substrate processing apparatus is provided that includes an ozonizer for generating ozone gas and an ozone sensor for detecting an ozone gas concentration. The substrate processing apparatus processes a substrate by using the ozone gas supplied from the ozonizer. The substrate processing apparatus includes a monitor unit for monitoring the ozone gas concentration detected by the ozone sensor and a control unit for detecting an abnormality of the ozone gas concentration based on the monitored ozone gas concentration and the monitored discharge power.

Abstract: A batch-type vertical substrate processing apparatus includes a processing chamber into which a substrate holder configured to stack and hold a plurality of target substrates in a height direction is inserted; and a plurality of flanges formed to protrude from an inner wall of the processing chamber toward an internal space of the processing chamber along a planar direction and configured to divide the interior of the processing chamber into a plurality of processing subspaces along the height direction, wherein the flanges include insertion holes through which the substrate holder is inserted, and diameters of the insertion holes are small at an upper side of the processing chamber and become gradually larger toward a lower side of the processing chamber.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.