Of Silicon Nitride (epo) Patents (Class 257/E21.293)
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Patent number: 8076251Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.Type: GrantFiled: September 29, 2010Date of Patent: December 13, 2011Assignee: Hitachi Kokusai Electric, Inc.Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
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Publication number: 20110300722Abstract: A substrate processing device comprises a reaction vessel 11 forming a space receiving a substrate 1 and adapted to have a plurality of reaction gases supplied thereto to perform desired processing of the substrate, an exhaust port 16 formed in the reaction vessel 11 for exhausting the reaction vessel 11, and a gas supply system 70A, 70B for supplying at least a plurality of reaction gases into the reaction vessel 11, the gas supply system 70A, 70B including a cleaning gas supply unit for supplying a cleaning gas to perform desired processing of the substrate 1 to thereby remove adherents in the reaction vessel 11, and a post-processing gas supply unit for supplying a post-processing gas capable of removing the elements contained in the cleaning gas remaining in the reaction vessel 11 after the adherents have been removed by supplying the cleaning gas, the post-processing gas containing all of the reaction gases used in performing desired processing of the substrate.Type: ApplicationFiled: June 8, 2011Publication date: December 8, 2011Inventors: Masanori Sakai, Nobuhito Shima, Kazuyuki Okuda
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Publication number: 20110266609Abstract: Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH4) flow, reducing the overall exposure of the structure to hydrogen radicals. This results in the silicon nitride being strongly bonded to the structure and in improved performance.Type: ApplicationFiled: June 21, 2011Publication date: November 3, 2011Inventors: Sung Jin KIM, Alexander NICKEL, Minh-Van NGO, Hieu Trung PHAM, Masato TSUBOI, Sinich IMADA
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Publication number: 20110256734Abstract: Described are methods of making SiN materials on substrates, particularly SiN thin films on semiconductor substrates. Improved SiN films made by the methods are also included.Type: ApplicationFiled: April 11, 2011Publication date: October 20, 2011Inventors: Dennis M. Hausmann, Jon Henri, Mandyam Sriram, Bart J. van Schravendijk
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Publication number: 20110254078Abstract: Provided is a method for depositing a silicon nitride film in a plasma CVD device which introduces microwaves into a process chamber by a planar antenna having a plurality of apertures, and the method including setting the pressure in the process chamber within a range from 10 Pa to 133.3 Pa and performing plasma CVD by using film formation gas including a silicon containing compound gas and a nitrogen gas while applying an RF bias to the wafer by supplying high-frequency power with an output density within a range from 0.009 W/cm2 to 0.64 W/cm2 per unit area of a wafer from a high frequency power supply to an electrode in a holding stage on which the wafer is arranged.Type: ApplicationFiled: June 20, 2011Publication date: October 20, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru HONDA, Masayuki KOHNO
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Patent number: 8039937Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.Type: GrantFiled: April 29, 2009Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Soo Chung, Seung-Kwan Ryu, Ju-Il Choi, Dong-Ho Lee, Seong-Deok Hwang
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Publication number: 20110244694Abstract: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower then silicon nitride.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventors: George Andrew Antonelli, Mandyam Sriram, Vishwanathan Rangarajan, Pramod Subramonium
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Patent number: 8030223Abstract: A solar cell (100) comprising a semiconductor solar cell substrate (66) having a light receiving surface formed on the first major surface and generating photovoltaic power based on the light impinging on the light receiving surface, wherein the light receiving surface of the semiconductor solar cell substrate (66) is coated with a light receiving surface side insulating film (61) composed of an inorganic insulating material where the cationic component principally comprising silicon, and the light receiving surface side insulating film (61) is a low hydrogen content inorganic insulating film containing less than 10 atm % of hydrogen. A solar cell having an insulating film exhibiting excellent passivation effect insusceptible to aging can thereby be provided.Type: GrantFiled: January 27, 2010Date of Patent: October 4, 2011Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Masatoshi Takahashi, Hiroyuki Ohtsuka, Hideki Matsumura, Atsushi Masuda, Akira Izumi
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Publication number: 20110223765Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.Type: ApplicationFiled: March 15, 2010Publication date: September 15, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Ryan YAMASE, Ji Ae PARK, Shamik PATEL, Thomas NOWAK, Zhengjiang "David" CUI, Mehul NAIK, Heung Lak PARK, Ran DING, Bok Hoen KIM
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Patent number: 8008214Abstract: In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.Type: GrantFiled: December 15, 2006Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Young-Jin Noh, Bon-Young Koo, Chul-Sung Kim, Hun-Hyeoung Leam, Woong Lee
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Patent number: 8008188Abstract: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.Type: GrantFiled: June 11, 2007Date of Patent: August 30, 2011Assignee: PPG Industries Ohio, Inc.Inventors: Kevin C. Olson, Alan E. Wang
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Patent number: 8003531Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.Type: GrantFiled: September 29, 2009Date of Patent: August 23, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 7999295Abstract: A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.Type: GrantFiled: December 17, 2008Date of Patent: August 16, 2011Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hang-Ting Lue, Kuang-Yeu Hsieh
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Publication number: 20110195582Abstract: A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide. These films are useful as dielectrics, passivation coatings, barrier coatings, spacers, liners and/or stressors in semiconductor devices.Type: ApplicationFiled: August 11, 2009Publication date: August 11, 2011Inventor: Xiaobing Zhou
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Patent number: 7989354Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.Type: GrantFiled: June 6, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Publication number: 20110183528Abstract: Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si3N4), siliconoxynitride (SioxNy) and/or silicon dioxide (SiO2). The precursors of the invention are amenable to use in low temperature (e.g., <500° C.) chemical vapor deposition processes, for fabrication of ULSI devices and device structures.Type: ApplicationFiled: March 22, 2011Publication date: July 28, 2011Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.Inventors: Ziyun Wang, Chongying Xu, Ravi K. Laxman, Thomas H. Baum, Bryan C. Hendrix, Jeffrey F. Roeder
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Patent number: 7985700Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.Type: GrantFiled: December 8, 2008Date of Patent: July 26, 2011Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 7985690Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: GrantFiled: June 4, 2009Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7981812Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.Type: GrantFiled: July 3, 2008Date of Patent: July 19, 2011Assignee: Applied Materials, Inc.Inventors: Kang-Lie Chiang, Chia-Ling Kao
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Patent number: 7981775Abstract: Provided is a nitride semiconductor light emitting diode and a method of manufacturing the same. The method includes sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, in-situ depositing a mask layer on a region of the surface of the second semiconductor layer, and selectively growing a third semiconductor layer formed in a textured structure on the second semiconductor layer by depositing a semiconductor material on the second semiconductor layer and the mask layer.Type: GrantFiled: December 28, 2005Date of Patent: July 19, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Suk-ho Yoon, Cheol-soo Sone
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Patent number: 7972941Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.Type: GrantFiled: July 1, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Hong, Gil-Heyun Choi, Jong-Myeong Lee, Geum-Jung Seong
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Publication number: 20110151679Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: Tokyo Electron LimitedInventors: Kazuhide HASEBE, Shigeru Nakajima, Jun Ogawa
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Patent number: 7956393Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: GrantFiled: September 21, 2009Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Sun-Young Hong, Young-Joo Choi, Byeong-Jin Lee, Nam-Seok Suh, Byung-Uk Kim, Suk-Il Yoon, Jong-Hyun Jeong, Sung-Gun Shin, Soon-Beom Huh, Se-Hwan Jung, Doo-Young Jang, Sun-Joo Park, Oh-Hwan Kweon
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Patent number: 7951685Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Sumitomo Chemical Company, LimitedInventors: Hiroyuki Sazawa, Naohiro Nishikawa, Masahiko Hata
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Patent number: 7947607Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.Type: GrantFiled: December 23, 2008Date of Patent: May 24, 2011Assignee: Macronix International Co., Ltd.Inventor: Chao-I Wu
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Patent number: 7939438Abstract: Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed.Type: GrantFiled: March 19, 2009Date of Patent: May 10, 2011Assignee: Rohm and Haas Electronic Materials LLCInventors: Gary Hamm, David L. Jacques, Carl J. Colangelo
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Patent number: 7939436Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.Type: GrantFiled: January 14, 2009Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Min-Sang Kim, Keun-Hwi Cho, Ji-Myoung Lee
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Patent number: 7927953Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.Type: GrantFiled: October 8, 2009Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Publication number: 20110086516Abstract: A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: ApplicationFiled: October 8, 2010Publication date: April 14, 2011Applicant: ASM JAPAN K.K.Inventors: Woo Jin Lee, Kuo-wei Hong, Akira Shimizu, Deakyun Jeong
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Publication number: 20110086517Abstract: Disclosed is a plasma CVD device. In the plasma CVD device, in producing a silicon nitride film while controlling the size of a band gap by CVD, microwaves are introduced into a treatment vessel by a flat antenna having a plurality of holes. The plasma CVD is carried out under a given treatment pressure selected from a pressure range of not less than 0.1 Pa and not more than 1333 Pa at a flow ratio between a silicon-containing compound gas and a nitrogen gas (silicon-containing compound gas flow rate/nitrogen gas flow rate) selected from a range of not less than 0.005 and not more than 0.2, whereby the Si/N ratio in the film is controlled to form a silicon nitride film having a band gap size of not less than 2.5 eV and not more than 7 eV.Type: ApplicationFiled: March 30, 2009Publication date: April 14, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Toshio Nakanishi, Masayuki Kohno, Tatsuo Nishita, Junya Miyahara
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Publication number: 20110076857Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing a predetermined element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.Type: ApplicationFiled: September 29, 2010Publication date: March 31, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Naonori AKAE, Yoshiro HIROSE, Yushin TAKASAWA, Yosuke OTA, Ryota SASAJIMA
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Patent number: 7910970Abstract: In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.Type: GrantFiled: June 20, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Mariko Takayanagi
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Publication number: 20110065289Abstract: There are provided a method of manufacturing a semiconductor device and a substrate processing apparatus by which the quality of a silicon nitride film can be improved. The method comprises: supplying a silicon-containing gas into a process chamber in which a substrate is accommodated in a heated state; and supplying a nitrogen-containing gas into the process chamber. The supplying of the silicon-containing gas and the supplying of the nitrogen-containing gas are alternately repeated to form a silicon nitride film on the substrate. The process chamber is switched at least once between an exhaust stop state and an exhaust operation state during the supplying of the nitrogen-containing gas so as to vary an inside pressure of the process chamber in a manner such that the maximum inside pressure of the process chamber is twenty or more times the minimum inside pressure of the process chamber.Type: ApplicationFiled: September 13, 2010Publication date: March 17, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventor: Masayuki ASAI
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Publication number: 20110065288Abstract: Provided is a substrate processing method comprising: loading a substrate, on which polysilazane is applied, into a substrate process chamber; maintaining an inside of the substrate process chamber, into which the substrate is loaded, in water vapor atmosphere and depressurization atmosphere at a temperature of 400° C.; performing a first heat treatment process on the substrate in a state where the inside of the substrate process chamber is maintained in the water vapor atmosphere and the depressurization atmosphere at the temperature of 400° C.; next, increasing an inner temperature of the substrate process chamber from the temperature of 400° C. in the first heat treatment process to a temperature ranging from 900° C. to 1000° C.; and performing a second heat treatment process on the substrate in a state where the inside of the substrate process chamber is maintained in water vapor atmosphere and depressurization atmosphere at the temperature ranging from 900° C. to 1000° C.Type: ApplicationFiled: August 17, 2010Publication date: March 17, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Toru HARADA, Masayoshi MINAMI
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Patent number: 7906439Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second regioType: GrantFiled: June 22, 2009Date of Patent: March 15, 2011Assignee: Commissarit a l'Energie AtomiqueInventors: François Perruchot, Bernard Diem, Vincent Larrey, Laurent Clavelier, Emmanuel Defay
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Patent number: 7902640Abstract: A dielectric layer including a film with silicon compound contain oxygen and a film with silicon compound contain nitrogen is provided. A ratio of Si—N group absorption intensity to a thickness of the film with silicon compound contain nitrogen in an FTIR spectrum is substantially greater than or substantially equal to 0.67/?m. The dielectric layer can be incorporated in switch devices.Type: GrantFiled: September 29, 2007Date of Patent: March 8, 2011Assignee: Au Optronics CorporationInventor: Chieh-Chou Hsu
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Patent number: 7902061Abstract: A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.Type: GrantFiled: August 27, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Louis C. Hsu, Carl Radens, Theodorus E. Standaert, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7902001Abstract: Provided is a sacrifice layer formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device.Type: GrantFiled: June 5, 2009Date of Patent: March 8, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang Jin Kim, Yongsoo Oh, Hwan-Soo Lee
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Patent number: 7897471Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.Type: GrantFiled: June 19, 2008Date of Patent: March 1, 2011Assignee: Fairchild Semiconductor CorporationInventor: Jifa Hao
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Publication number: 20110042728Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.Type: ApplicationFiled: August 18, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Charles William Koburger, III
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Patent number: 7884035Abstract: We have discovered that adding H2 to a precursor gas composition including SiH4, NH3, and N2 is effective at improving the wet etch rate and the wet etch rate uniformity across the substrate surface of a-SiNx:H films which are deposited on a substrate by PECVD. Wet etch rate is an indication of film density. Typically, the lower the wet etch rate, the denser the film. The addition of H2 to the SiH4/NH3/N2 precursor gas composition did not significantly increase the variation in deposited film thickness across the surface of the substrate. The uniformity of the film across the substrate enables the production of flat panel displays having surface areas of 25,000 cm2 and larger.Type: GrantFiled: April 11, 2008Date of Patent: February 8, 2011Assignee: Applied Materials, Inc.Inventors: Beom Soo Park, Soo Young Choi, Tae Kyung Won, John M. White
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Patent number: 7875912Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of Zrx Hfy Sn1-x-y O2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.Type: GrantFiled: May 23, 2008Date of Patent: January 25, 2011Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20110014795Abstract: A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.Type: ApplicationFiled: July 8, 2010Publication date: January 20, 2011Applicant: ASM JAPAN K.K.Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu
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Patent number: 7871926Abstract: A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the at least one feature is removed at a first rate and a second portion of the nitrogen-containing layer over the substrate adjacent to a bottom region of the at least one feature is removed at a second rate. The first rate is greater than the second rate. A dielectric layer is formed over the nitrogen-containing dielectric layer.Type: GrantFiled: October 22, 2007Date of Patent: January 18, 2011Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Mihaela Balseanu, Victor Nguyen, Derek R. Witty, Hichem M'Saad, Haichun Yang, Xinliang Lu, Chien-Teh Kao, Mei Chang
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Patent number: 7871940Abstract: A silicon nitride thin film formation apparatus is provided for stationary and moving substrates and a process for forming such films. The process provides high uniformity of film thickness and film properties as well as a high deposition rate. The film properties are adequate for application as an antireflection layer or passivation layer in solar cell devices or as dielectric layer in thin film transistors. The apparatus includes a number of metal filaments. In the space within the formation apparatus opposite to the substrate with respect to the filaments, a gas dosage system is arranged at a predetermined distance of the filaments. The film formation apparatus for stationary substrates also contains a shutter to control the starting and ending conditions for film formation and to control the film thickness.Type: GrantFiled: March 3, 2005Date of Patent: January 18, 2011Assignee: Universiteit Utrecht Holding B.V.Inventors: Rudolf Emmanuel Isidore Schropp, Catharina Henriette Maria Van Der Werf, Bernd Stannowski
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Patent number: 7867918Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.Type: GrantFiled: March 11, 2008Date of Patent: January 11, 2011Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Publication number: 20100323529Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface; a step of performing first nitriding to the silicon exposed on the surface of the substrate, and forming a silicon nitride film having a thickness of 0.2 nm but not more than 1 nm on the surface of the substrate; and a step of performing first heat treatment to the silicon nitride film in N2O atmosphere and forming a silicon nitride film. This method may further include a step of performing second nitriding to the silicon oxynitride film, and furthermore, may include a step of performing second heat treatment to the silicon oxynitride film after the second nitriding.Type: ApplicationFiled: December 20, 2007Publication date: December 23, 2010Applicant: Tokyo Electron LimitedInventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
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Publication number: 20100320548Abstract: A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C.). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.Type: ApplicationFiled: June 10, 2010Publication date: December 23, 2010Applicant: ANALOG DEVICES, INC.Inventors: Christine H. Tsau, Thomas Kieran Nunan
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Patent number: 7855404Abstract: A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.Type: GrantFiled: December 1, 2004Date of Patent: December 21, 2010Assignee: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Instituit fur Innovative MikroelektronikInventors: Bernd Heinenman, Jürgen Drews, Steffen Marschmayer, Holger Rücker
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Publication number: 20100304574Abstract: Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism.Type: ApplicationFiled: August 6, 2010Publication date: December 2, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Nobutake NODERA, Masanobu Matsunaga, Kazuhide Hasebe, Koto Umezawa, Pao-Hwa Chou