Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device includes a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.

Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

Abstract: After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.

Abstract: A production method for a semiconductor device comprising the first step of supplying a first reaction material to a substrate housed in a processing chamber to subject to a ligand substitution reaction a ligand as a reaction site existing on the surface of the substrate and the ligand of the first reaction material, the second step of removing the excessive first reaction material from the processing chamber, the third step of supplying a second reaction material to the substrate to subject a ligand substituted by the first step to a ligand substitution reaction with respect to a reaction site, the fourth step of removing the excessive second reaction material from the processing chamber, and a fifth step of supplying a third reaction material excited by plasma to the substrate to subject a ligand, not subjected to a substitution reaction with respect to a reaction site in the third step, to a ligand substitution reaction with respect to a reaction site, wherein the steps 1-5 are repeated a specified number

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.

Abstract: A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors.

Abstract: An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact structures and the inter-level insulation layer. Second spacers are disposed between the second contact structures and the inter-level insulation layer. Metal interconnections are disposed on the inter-level insulation layer and connected to the first and second contact structures. The first contact structures include first and second plugs stacked in sequence, the second contact structures include the second plugs, and the first spacers include an upper spacer disposed between the second plug and the inter-level insulation layer.

Abstract: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.

Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openin

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.

Abstract: Provided is a silicon nitride film which has an excellent charge storage capacity and thus is useful as a charge storage layer of a semiconductor memory device. The silicon nitride film having substantially uniform trap density in the film thickness direction has high charge storage performance. The silicon nitride film is formed by plasma CVD by using a plasma processing apparatus (100), wherein microwaves are introduced into a chamber (1) by a plane antenna having a plurality of holes, plasma is generated by the microwaves while a source gas including nitrogen-containing compound and silicon-containing compound is introduced into the chamber (1), and the silicon nitride film is deposited on the surface of a processing object by the plasma.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.

Abstract: Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Abstract: The present invention is a method to increase the intrinsic compressive stress in plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) and silicon carbonitride (SiCN) thin films, comprising depositing the film from an amino vinylsilane-based precursor. More specifically the present invention uses the amino vinylsilane-based precursor selected from the formula: [RR1N]xSiR3y(R2)z, where x+y+z=4, x=1-3, y=0-2, and z=1-3; R, R1 and R3 can be hydrogen, C1 to C10 alkane, alkene, or C4 to C12 aromatic; each R2 is a vinyl, allyl or vinyl-containing functional group.

Abstract: In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa.

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract: A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.

Abstract: A semiconductor device of an embodiment can prevent nitriding of the lower-layer insulating film and oxygen diffusion from the upper-layer insulating film, so as to minimize the decrease in charge capture density. This semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a nitrogen-added amorphous silicon layer formed on the first insulating film, a first silicon nitride layer formed on the amorphous silicon layer, and a second insulating film formed above the first silicon nitride layer.

Abstract: Provided is a method of manufacturing a semiconductor device including at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: A method of forming an ultra-thin SiN film includes: supplying a Si source gas into a reactor in which a substrate is placed on a susceptor; supplying an N source gas into the reactor at a flow rate which is at least 300 times that of the Si source gas; applying an RF power between an upper electrode and the susceptor in the reactor; and depositing an ultra-thin SiN film on the substrate.

Abstract: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.

Abstract: A method and apparatus for igniting a gas mixture into plasma using capacitive coupling techniques, shielding the plasma and other contents of the plasma reactor from the capacitively-coupled electric field, and maintaining the plasma using inductive coupling are provided. For some embodiments, the amount of capacitive coupling may be controlled after ignition of the plasma. Such techniques are employed in an effort to prevent damage to the surface of a substrate from excessive ion bombardment caused by the highly energized ions and electrons accelerated towards and perpendicular to the substrate surface by the electric field of capacitively-coupled plasma.

Abstract: A manufacturing method for semiconductor devices having MOSFET gate insulation films The method includes forming a silicon oxide film, forming a silicon nitride film, nitriding the silicon nitride film, and first and second heat treatments.

Abstract: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.

Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.

Abstract: A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.

Abstract: A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.

Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer oxide layer and a nitride layer on the oxide layer.

Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.

Abstract: A method for using a film formation apparatus includes, in order to inhibit metal contamination: performing a cleaning process using a cleaning gas on an inner wall of a process container and a surface of a holder with no productive target objects held thereon; and then, performing a coating process of forming a silicon nitride film by alternately supplying a silicon source gas and a nitriding gas to cover with the silicon nitride film the inner wall of the process container and the surface of the holder with no productive target objects held thereon.

Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.

Abstract: A method for forming an insulating film includes forming a silicon nitride film on a silicon surface by subjecting a target substrate wherein silicon is exposed in the surface to a treatment for nitriding the silicon, forming a silicon oxynitride film by heating the target substrate provided with the silicon nitride film in an N2O atmosphere, and nitriding the silicon oxynitride film.

Abstract: A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, the stress material inside the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A first conductive layer is filled into the contact opening to form a contact.

Abstract: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may protrude through the top surface of the oxide after CMP, the spacers serve to prevent possible later shorting to the stack.

Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

Abstract: A vertical plasma processing apparatus for a semiconductor process for performing a plasma process on target substrates all together includes an exciting mechanism configured to turn at least part of a process gas into plasma. The exciting mechanism includes first and second electrodes provided to a plasma generation box and facing each other with a plasma generation area interposed therebetween, and an RF power supply configured to supply an RF power for plasma generation to the first and second electrodes and including first and second output terminals serving as grounded and non-grounded terminals, respectively. A switching mechanism is configured to switch between a first state where the first and second electrodes are connected to the first and second output terminals, respectively, and a second state where the first and second electrodes are connected to the second and first output terminals, respectively.

Abstract: A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least the silicon surface serving as a light-receiving portion of a photodiode is exposed, and a process of depositing a silicon nitride film on the silicon oxide film. At least the silicon oxide film and the silicon nitride film are finally left on the surface of the photodiode as an antireflection film.