Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

Abstract: In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

Abstract: A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.

Abstract: There is provided a method for manufacturing a semiconductor device which is capable of stably forming a plated layer on a plating base layer while adhered chippings are reduced. The method includes forming an insulating film covering at least a base metal on a diffusion region of a semiconductor substrate, forming an organic coating film having an opening at least at a surface section of the base metal being to be exposed on the insulating film, pasting a surface protection tape on the semiconductor substrate to cover the insulating film and the organic coating film, polishing a back surface of the semiconductor substrate that opposes the base metal, removing the surface protection tape, etching the insulating film with the organic coating film used as a mask to expose the base metal and forming a conductive plated layer on the base metal.

Abstract: A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film.

Abstract: A method of removing photoresist from a surface during the manufacture of an integrated circuit. Organometallic polymers and monomers are formed during the etch of a hard mask material defining the locations of a metal-bearing film, such as tantalum nitride, when photoresist is used to mask the hard mask etch. These organometallic polymers and monomers as formed are not fully cross-linked. A liquid phase solution of sulfuric acid and hydrogen peroxide used to remove the photoresist also removes these not-fully-cross-linked organometallic polymers and monomers, thus preventing the formation of stubborn contaminants during subsequent high temperature processing.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

Abstract: A substrate is secured on a chuck that maintains a top surface of the substrate in a substantially level orientation. The chuck is positioned within a cavity of a vessel such that a body portion of the chuck is maintained in a spaced apart relationship with a surface of the cavity. An electroless plating solution is disposed in a region between the body portion of the chuck and the surface of the cavity such that an upper surface of the electroless plating solution is at a level lower than the substrate. The chuck is lowered within the cavity to cause the electroless plating solution to be displaced upward and flow over the top surface of the substrate in a substantially uniform manner from a periphery of the substrate to a center of the substrate. The chuck is then raised such that the electroless plating solution flows off of the substrate.

Abstract: The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.

Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. Nanowires having a predetermined diameter and a predetermined position can be grown from the nanoparticles.

Abstract: Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO4) as a ruthenium precursor. In some embodiments for forming ruthenium, methods include forming a seed layer, and forming a ruthenium layer on the seed layer, using RuO4. In other embodiments, methods include performing atomic layer deposition cycles, which include using RuO4 and another ruthenium-containing co-precursor. In yet other embodiments, methods include adsorbing a reducing agent over a substrate, and supplying RuO4 to be reduced to ruthenium by the adsorbed reducing agent. In other embodiments for forming ruthenium dioxide, methods may include providing an initial seed layer formed of, for example, an organic compound, and supplying RuO4 over the seed layer.

Abstract: A method of forming a resist pattern on a silicon semiconductor substrate having an anti-reflective layer thereon is described. The method includes the steps of a) modifying surface energy of the anti-reflective surface with a chemical treatment composition, b) applying a UV etch resist to the treated anti-reflective surface, and c) exposing the anti-reflective surface to a wet chemical etchant composition to remove exposed areas of the anti-reflective surface. Thereafter, the substrate can be metallized to provide a conductor pattern. The method may be used to produce silicon solar cells.

Abstract: An object including at least one graphic element, including at least one layer including at least one metal and etched according to a pattern of the graphic element, a first face of the layer being positioned opposite a face of at least one at least partly transparent substrate, a second face, opposite to the first face, of the layer being covered with at least one passivation layer fixed to at least one face of at least one support by wafer bonding and forming with the support a monolithic structure, and the layer including at least at the second face, at least one area including the metal and at least one semiconductor.

Abstract: A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.

Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.

Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.

Abstract: The disclosure discloses a method for making a conductive film and a film making equipment. The method includes providing a substrate having two opposite straight sides, a first side connecting the straight sides, and a second side connecting the straight sides and opposite to the first side. A film layer structure is formed on the substrate. A conductive film is formed by pulling out the film layer structure through the first side of the substrate.

Abstract: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.

Abstract: Disclosed is a method for making semiconductor electrodes. In the method, there is provided a wafer. The wafer includes at least one conductive unit, a plurality of first connective units connected to the conductive unit, a plurality of first metal layers connected to the first connective units and a plurality of second connective units connected to the first metal layers. Photo-resist is provided on the first and second connective units. A second metal layer is provided on each of the first metal layers via using an electroplating device. The wafer is cut from the photo-resist, thus forming semiconductor electrodes.

Abstract: Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

Abstract: [Problems] There is provided a metal oxide film forming method capable of controlling a film thickness of a metal oxide even if the metal oxide is subject to a self-limited thickness. [Means for Solving the Problems] A metal oxide film forming method includes a process (1) of supplying a metal source gas to a surface of a base before a temperature of the base reaches a film formation temperature of a metal oxide film; and a process (2) of setting the temperature of the base to be equal to or higher than the film formation temperature and forming the metal oxide film on the base by making a reaction between the metal source gas supplied to the surface of the base and residual moisture on the surface of the base.

Abstract: Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped and are prevented from migrating and agglomerating. The adhesion layer can include between about 20-80% atomic of copper. The copper atoms of the adhesion layer are exposed during deposition of a copper seed layer and serve as the nucleation sites for the deposited copper. Thin, continuous, and conformal seed layers can be deposited on top of the adhesion layer. The trapping of copper within the adhesion layer is achieved by intermixing diffusion barrier and seed layer materials using PVD and/or ALD.

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.

Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.

Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.

Abstract: A method for fabricating a contact (240) for a solar cell (200). The method includes providing a solar cell substrate (210) with a surface that is covered or includes an antireflective coating (220). For example, the substrate (210) may be positioned adjacent or proximate to an outlet of an inkjet printer (712) or other deposition device. The method continues with forming a burn through layer (230) on the coating (220) by depositing a metal oxide precursor (e.g., using an inkjet or other non-contact printing method to print or apply a volume of liquid or solution containing the precursor). The method includes forming a contact layer (240) comprising silver over or on the burn through layer (230), and then annealing is performed to electrically connect the contact layer (240) to the surface of the solar cell substrate (210) through a portion of the burn through layer (230) and the coating (220).

Abstract: A TiN film is formed by a first step of forming a TiN intermediate film on a wafer by supplying TiCl4 and NH3 reacting with TiCl4 to the wafer and controlling a processing condition for causing a bonding branch that has not undergone a substitution reaction to remain at a predetermined concentration at a part of TiCl4 and a second step of substituting the bonding branch contained in the TiN intermediate film by supplying H2 to the wafer, the first step and the second step being performed in this order.

Abstract: Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of supplying a source into a processing chamber in which the substrate is accommodated and exhausting the source and a process of supplying a first oxidizing source into the processing chamber and exhausting the first oxidizing source; and a second high permittivity insulation film is formed on the first high permittivity insulation film by alternately repeating a process of supplying the source into the processing chamber and exhausting the source and a process of supplying a second oxidizing source different from the first oxidizing source into the processing chamber and exhausting the second oxidizing source.

Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates. In one embodiment, a method of the present invention comprises heating a porous silicon deposition surface of a porous silicon substrate to a temperature operable for epitaxial deposition of at least one atom or molecule, contacting the porous silicon deposition surface with a reactive gas mixture comprising at least one chemical species comprising a group IV element and at least one silicon chemical species, and depositing a silicon-group IV element layer on the porous silicon deposition surface. In another embodiment, the chemical species comprising a group IV element can be replaced with a transition metal species to form a silicon silicide layer.

Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.

Abstract: A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Abstract: Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times.

Abstract: A device that includes a signal generating unit having a surface that can receive photons, a first metal structure located on the surface of the signal generating unit, and a second metal structure located on the surface of the signal generating unit. The second metal structure being spaced apart from the first metal structure.

Abstract: A semiconductor device comprises gates comprising a first conductive layer, landing plug contacts formed adjacent to the gate and formed of a second conductive layer, a bit line formed over the landing plug contacts and formed of a third conductive layer, and storage electrode contacts formed over the landing plug contacts and the bit line and formed of a fourth conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are made of the same material.

Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

Abstract: A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance.

Abstract: A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular.

Abstract: Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.

Abstract: A display includes: a light-emitting element formed by laminating a first electrode layer, an organic layer including a light-emitting layer and a second electrode layer in order on a base; and an auxiliary wiring layer being arranged so as to surround the organic layer and being electrically connected to the second electrode layer, in which the auxiliary wiring layer includes a two-layer configuration including a first conductive layer and a second conductive layer, the first conductive layer has lower contact resistance to the second electrode layer than that of the second conductive layer, the two-layer configuration in the auxiliary wiring layer is formed so that an end surface of the second conductive layer is recessed inward from an end surface of the first conductive layer, thereby a part of a top surface of the first conductive layer is in contact with the second electrode layer.

Abstract: A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: Metal pastes comprising (a) at least one electrically conductive metal powder selected from the group consisting of silver, copper and nickel, (b) at least one lead-free glass frit with a softening point temperature in the range of 550 to 611° C. and containing 11 to 33 wt.-% of SiO2, >0 to 7 wt.-% of Al2O3 and 2 to 10 wt.-% of B2O3 and (c) an organic vehicle.