Abstract: An aspect of the present invention, there is provided a method for providing a coating-type film, including, coating a solution including an organic metal compound on a surface of a substrate including a semiconductor substrate to form a coating film, heating the coating film to volatize a solvent in the coating film, and performing a treatment including at least one of a heat treatment, an ozone treatment and a moisture treatment to remove impurities from the coating film.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to, the following processes. A conductive film is formed over a semiconductor substrate. First and second photo resist patterns are formed on the conductive film. A space is located between the first and second photo resist patterns. An insulating mask is formed by using catalytic reaction so as to cover surfaces of the first and second photo resist patterns. The insulating mask protects the surfaces of the first and second photo resist patterns. A part of the conductive film is etched by using the insulating mask on the first and second photo resist patterns as an etching mask.

Abstract: A method for manufacturing a photovoltaic cell, such as a solar cell is disclosed. The method includes: providing a silicon substrate; applying to a side of the silicon substrate, a first layer of a metal with a relatively high optical reflectance, such as a layer of silver; applying to the first layer, a second layer of a metal with a relatively high electrical conductivity coefficient, such as a layer of aluminum or an Al alloy; and then firing the substrate having the first and second layers in order to obtain an alloy of the metals of the first and second layers and the silicon, wherein the alloy formed comprises a maximum amount of metal dissolved in the silicon in amounts up to the eutectic point of the alloy. In one implementation, the alloy is substantially an n-type Si—Al—Ag alloy. Thus, an improved Back Surface Field is formed in the substrate. The invention further relates to a photo voltaic cell obtained with the aid of such method.

Abstract: A film formation method to form a predetermined thin film on a target substrate includes first and second steps alternately performed each at least once. The first step is arranged to generate first plasma within a process chamber that accommodates the substrate while supplying a compound gas containing a component of the thin film and a reducing gas into the process chamber. The second step is arranged to generate second plasma within the process chamber while supplying the reducing gas into the process chamber, subsequently to the first step.

Abstract: A method of forming the multi metal layers thin film has Ti sputtered on top surface of a substrate by PVD first. Then, Ti is transformed into TiN via CVD. Thus, by skipping the extra process steps of wafer cleaning and surface treating, the method not only solves the stress problems between two different metal layers but also improves the cycle time and particle performance for the production without any yield impact.

Abstract: This invention relates to method of forming a thin film on a substrate in a reaction chamber by an atomic layer deposition process comprising a plurality of individual cycles. The plurality of individual cycles comprise at least two groupings of individual cycles.

Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.

Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.

Abstract: A method of fabricating a carbon nanotube array sensor includes the following steps. A carbon nanotube array, a first electrode and a second electrode are provided, the carbon nanotube array includes a plurality of carbon nanotubes. Each of the carbon nanotubes includes a first end and a second end opposite to the first end. A first metallophilic layer is formed on the first end of each of the carbon nanotubes. At least one first conductive metal layer is arranged between the first metallophilic layer and the first electrode to electrically connect each of the carbon nanotubes with the first electrode. A second metallophilic layer is formed on the second end of each of the carbon nanotubes. At least one second conductive metal layer is arranged between the second metallophilic layer and the second electrode to electrically connect each of the carbon nanotubes with the second electrode.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a ruthenium (Ru) film at least on a bottom surface of the opening; and filling in the opening with a tungsten (W) film in which the Ru film is formed, according to a chemical vapor deposition (CVD) method by hydrogen (H2) reduction.

Abstract: A method for fabricating a semiconductor includes the steps of forming a porous insulation film and wires on a substrate, the wires embedded in the porous insulation film having a portion adjacent to the wires and a remote portion spaced apart from the wires; and applying an energy beam to the remote portion to change the structure of the porous insulation film such that an Young's modulus of the porous insulation film increased so as to substantially reinforce the strength of the porous insulation film.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.

Abstract: Alternative methods of constructing a vertically offset structure are disclosed. An embodiment includes forming a flexible layer having first and second end portions, an intermediate portion coupling the first and second portions, and upper and lower surfaces. The distance between the upper and lower surfaces at the intermediate portion is less than the distance between the upper and lower surfaces at the first and second end portions. The first end portion is bonded to a base member. The second end portion of the flexible layer is deflected until the second end portion contacts the base member. The second end portion is bonded to the base member.

Abstract: A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.

Abstract: Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process.

Abstract: Compositions and methods for forming a metal-containing thin film on a substrate. A reactor and at least one substrate in the reactor are provided. A metal-containing bis-?-diketiminate precursor is introduced into the reactor. The reactor is maintained at a set temperature and pressure, and the precursor is contacted with the substrate to form a metal-containing film on the substrate.

Abstract: The disclosure relates to a method for producing a multi-beam deflector array device with a plurality of openings for use in a particle-beam exposure apparatus, in particular a projection lithography system, said method starting from a CMOS wafer and comprising the steps of generating at least one pair of parallel trenches on the first side of the wafer blank at the edges of an area where the circuitry layer below is non-functional, the trenches reaching into the layer of bulk material; passivating the sidewalls and bottom of the trenches; depositing a conducting filling material into the trenches, thus creating columns of filling material serving as electrodes; attaching metallic contact means to the top of the electrodes; structuring of an opening between the electrodes, said opening stretching across abovementioned area so that the columns are arranged opposite of each other on the sidewalls of the opening.

Abstract: A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer.

Abstract: Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.

Abstract: A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film pattern, and etching a lower portion of the thin film pattern selectively using the protection layer as a mask to increase the first bottom widths of the depression portions into second bottom widths.

Abstract: The conductive paste contains a conductive metal powder and an organic vehicle. The conductive paste has characteristics that the viscosity falls within the range of 200 Pa·s to 350 Pa·s when the shear rate of 10 s?1 is applied and within the range of 80 Pa·s to 120 Pa·s when the shear rate of 40 s?1 is applied under 25° C. and magnitudes of a storage elastic modulus G? and a loss elastic modulus G? are reversed when distortion applied to the conductive paste at the frequency of 1 Hz is varied from 0 to 20%.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.

Abstract: One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.

Abstract: A method for manufacturing a semiconductor power device may includes: performing a grinding process on a back side of a wafer, performing a first plasma process and a rapid thermal process sequentially after performing the grinding process, performing a second plasma process after performing the rapid thermal process, and performing a metal thin film process after performing the second plasma process. The method for manufacturing a semiconductor device may be capable of preventing a peeling effect from occurring on a wafer surface by removing hydrogen from the wafer surface by controlling surface roughness to a desired level by treating the wafer surface using hydrogen plasma and a rapid thermal process (RTP) after subjecting a backside of the wafer to a grinding process.

Abstract: A method of controlling the resistivity and morphology of a tungsten film is provided, comprising depositing a first film of a bulk tungsten layer on a substrate during a first deposition stage by (i) introducing a continuous flow of a reducing gas and a pulsed flow of a tungsten-containing compound to a process chamber to deposit tungsten on a surface of the substrate, (ii) flowing the reducing gas without flowing the tungsten-containing compound into the chamber to purge the chamber, and repeating steps (i) through (ii) until the first film fills vias in the substrate surface, increasing the pressure in the process chamber, and during a second deposition stage after the first deposition stage, depositing a second film of the bulk tungsten layer by providing a flow of reducing gas and tungsten-containing compound to the process chamber until a second desired thickness is deposited.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract: A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.

Abstract: A substrate carrier is used in an in-line fabrication such as Plasma Enhanced Chemical Vapor Deposition (PECVD) for application of thin film on substrates. The carrier is in thermal communication with the substrate and thereby provides heat sinking. The carrier further permits movement of the substrate past a deposition apparatus at a deposition station.

Abstract: A probe card is includes a wafer and a plurality of needle patterns penetrating the wafer. The needle patterns are configured to supply an electrical signal for testing a separate wafer. The probe card may be mounted to a printed circuit board in a manner in which conductive patterns of the probe card are electrically connected to conductive terminals of the printed circuit board. The needle patterns may protrude from a lower end of the wafer and be formed so that an interval between needle patterns is the same as an interval between pads of a wafer to be tested.

Abstract: A truss structure is provided. The truss structure comprises a substrate; and plural sub-truss groups disposed on the substrate, wherein each sub-truss group comprises plural VIAs; and plural metal layers interlaced with the plural VIAs, wherein the plural sub-truss groups are piled up on each other to form a 3-D corrugate structure.

Abstract: A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance.

Abstract: Methods of promoting adhesion between a reflective backing layer and a solar cell substrate are provided. The reflective backing layer is formed over a conductive metal oxide layer as an alloy using reflective and adhesive components, the adhesive components being present in levels generally below about 5 atomic percent. Techniques are disclosed for depositing varying the concentration of the reflective backing layer to localize the adhesive components in an adhesion region near the conductive metal oxide layer. Techniques are also disclosed for boosting bonding species in the conductive metal oxide layer to further enhance adhesion.

Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

Abstract: Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned double patterning (SADP) process. A conformal layer of non-sacrificial material is formed over features of sacrificial structural material patterned near the optical resolution of a photolithography system using a high-resolution photomask. An anisotropic etch of the non-sacrificial layer leaves non-sacrificial ribs above a substrate. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features. No hard mask is needed to form the non-sacrificial ribs, reducing the number of processing steps involved.

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract: The invention relates to a method for fabricating a layer comprising nickel monosilicide NiSi on a substrate comprising silicon successively comprising the following steps: a) a step of incorporating, on a portion of the thickness of the said substrate comprising silicon, an element selected from W, Ti, Ta, Mo, Cr and mixtures thereof; b) a step of depositing, on the said substrate obtained in step a), a layer of nickel and a layer of an element selected from Pt, Pd, Rh and mixtures thereof or a layer comprising both nickel and an element selected from Pt, Pd, Rh and mixtures thereof; c) a step of heating to a temperature sufficient for obtaining the formation of a layer comprising nickel silicide optionally in the form of nickel monosilicide NiSi; d) a step of incorporating fluorine in the said layer obtained in c); and e) optionally, a step of heating to a sufficient temperature to convert the layer mentioned in d) to a layer comprising nickel silicide entirely in the form of nickel monosilicide NiSi.

Abstract: A dielectric film production process comprising a baking step in which a dielectric film is formed by heating a precursor layer formed on a metal layer, wherein the metal layer contains at least one type of metal selected from the group consisting of Cu, Ni, Al, stainless steel and austenitic nickel-chromium-based superalloy and during at least part of the baking step the precursor layer is heated in a reduced pressure atmosphere.

Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

Abstract: Methods for performing periodic plasma annealing during atomic layer deposition are provided along with structures produced by such methods. The methods include contacting a substrate with a vapor-phase pulse of a metal source chemical and one or more plasma-excited reducing species for a period of time. Periodically, the substrate is contacted with a vapor phase pulse of one or more plasma-excited reducing species for a longer period of time. The steps are repeated until a metal thin film of a desired thickness is formed over the substrate.

Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.

Abstract: Removal compositions and processes for removing at least one material layer from a rejected microelectronic device structure having same thereon. The removal composition includes hydrofluoric acid. The composition achieves substantial removal of the material(s) to be removed while not damaging the layers to be retained, for reclaiming, reworking, recycling and/or reuse of said structure.

Abstract: A method for the vapor deposition of aluminum films is provided. Such method employs a dialkyl amido dihydroaluminum compound of the formula [H2AlNR1R2]n wherein R1 and R2 are the same or different alkyl groups having 1 to 3 carbons, and n is an integer of 2 or 3. The aluminum films may be thick or thin and may be aluminum films or may be mixed metal films with aluminum metal. Both CVD and ALD methods may be employed.

Abstract: There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing method includes: an etching process for etching a low dielectric insulating film formed on a substrate; a CO2 plasma process for exposing the substrate to CO2 plasma after the etching process; and a UV process for irradiating UV to the low dielectric insulating film after the CO2 plasma process.

Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.

Abstract: Metal nanoplates are grown on n-type and p-type semiconductor wafer substrates through galvanic reactions between substantially pure aqueous metal solutions and the substrates. The morphology of the resulting metal nanoplates that protrude from the substrate can be tuned by controlling the concentration of the metal solution and the reaction time of the solution with the semiconductor wafer. Nanoplate size gradually increases with prolonged growth time and the nanoplate thicknesses increases in a unique stepwise fashion due to polymerization and fusion of adjacent nanoplates. Further, the roughness of the nanoplates can also be controlled. In a particular embodiment, Ag nanoplates are grown on a GaAs substrate through reaction with a solution of AgNO3 with the substrate.

Abstract: A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line.

Abstract: A method for manufacturing a semiconductor device having a damascene metal/insulator/metal (MIM)-type capacitor and metal lines including providing a semiconductor device; sequentially forming a first interlayer insulating film and a second interlayer insulating film over the semiconductor substrate; simultaneously forming a vias hole and a lower metal line in a line region and a lower electrode in a capacitor region, wherein the lower metal line and the lower electrode are electrically connected to the semiconductor device; sequentially forming a dielectric film, a third interlayer insulating film, a fourth interlayer insulating film and a fifth interlayer insulating film over the semiconductor substrate; and then simultaneously forming a plurality of upper electrodes, a plurality of second vias holes and a plurality of second upper metal lines in the capacitor region electrically connected to the plurality of upper electrodes, a plurality of third vias holes and a plurality of second upper metal lines in th

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).