Characterized By The Implantation Of Both Electrically Active And Inactive Species In The Same Semiconductor Region To Be Doped (epo) Patents (Class 257/E21.343)
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Patent number: 8778717Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.Type: GrantFiled: March 17, 2010Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Shang Hsiao, Chung-Te Lin, Nai-Wen Cheng, Yin-Kai Liao, Wei Chuang Wu
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Patent number: 8735234Abstract: An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is applied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed.Type: GrantFiled: February 16, 2011Date of Patent: May 27, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Atul Gupta, Nicholas Bateman
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Patent number: 7980198Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.Type: GrantFiled: April 7, 2010Date of Patent: July 19, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Naoto Yamade
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Patent number: 7923359Abstract: There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.Type: GrantFiled: September 28, 2005Date of Patent: April 12, 2011Assignee: NXP B.V.Inventors: Wolfgang Euen, Stephan Gross
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Patent number: 7898062Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: GrantFiled: April 9, 2010Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7713761Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.Type: GrantFiled: May 18, 2007Date of Patent: May 11, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Naoto Yamade
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Patent number: 7705429Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: GrantFiled: February 2, 2009Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7592243Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.Type: GrantFiled: October 28, 2005Date of Patent: September 22, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Youichi Momiyama, Kenichi Okabe, Takashi Saiki, Hidenobu Fukutome
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Patent number: 7489019Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: GrantFiled: July 6, 2006Date of Patent: February 10, 2009Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7320921Abstract: A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.Type: GrantFiled: March 22, 2005Date of Patent: January 22, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Wang, Ta-Wei Wang
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Patent number: 7301221Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.Type: GrantFiled: August 31, 2005Date of Patent: November 27, 2007Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 7297617Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.Type: GrantFiled: April 22, 2003Date of Patent: November 20, 2007Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 7250312Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.Type: GrantFiled: August 4, 2004Date of Patent: July 31, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Naoto Yamade
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Patent number: 7163878Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).Type: GrantFiled: November 4, 2005Date of Patent: January 16, 2007Assignee: Texas Instruments IncorporatedInventors: Puneet Kohli, Mark Rodder, Rick Wise, Amitabh Jain